MCP19035-AAAAESLASHMF datasheet(28/44 Pages) MICROCHIP

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MCP19035

DS22326B-page 28

 2012-2013 Microchip Technology Inc.

6.0.2

INPUT CAPACITOR SELECTION

The converter operates with a maximum duty cycle of

22.5%. A ceramic capacitor (X7R dielectric) with a

10 m

 ESR (typical) will be used. The minimum

capacitance

for

input

capacitor,

calculated

Equation 5-4, is 32.7 µF. Use two standard 22 µF

capacitors (X7R) rated at 25VDC in parallel.

6.0.3

OUTPUT CAPACITOR SELECTION

Based on a step load from 25% to 75% of the maximum

output current, the minimum value for the output capac-

itor can be determined with Equation 5-7. The mini-

mum value is 456 µF. Choose the next higher standard

value (500 µF). The ESR of the output capacitor will

strongly affect the output voltage ripple. Use five

100 µF standard ceramic capacitors (X7R or X5R

dielectric) rated at 6.3VDC in parallel. The estimated

final value of the ESR is lower than 5 m

. The output

voltage ripple is now estimated with Equation 5-6.

6.0.4

MOSFETS SELECTION

Before the MOSFET selection, the total losses of the

converter should be estimated. For this application, the

input power can be estimated using Equation 6-1:

EQUATION 6-1:

INPUT POWER

The total power losses are estimated in Equation 6-2:

EQUATION 6-2:

TOTAL CONVERTER

LOSSES

To achieve the efficiency goal (90%), the total power

losses must be lower than 2W at 10A output current.

Table 6-3 shows how these losses are distributed over

the converter components. The power losses distribu-

tion varies with the design parameters. As a rule of

thumb, for designs that have higher conversion ratio

(low duty cycles), the losses for the high-side MOSFET

are mainly switching losses. For the low side, most of

the losses will be the conduction losses.

An important part of the total power losses (over 75%)

are dissipated by the MOSFETs.

For the high-side MOSFET, the total amount of losses

(conduction and switching losses) should not exceed

0.72W. This design has a higher conversion ratio

(greater than 7:1), thus most of the losses of the high-

side MOSFET will be switching losses. As a rule of

thumb, the switching losses will be considered to be

70% of the total losses.

The conduction losses for the high-side MOSFET are

estimated in Equation 5-10. High-side MOSFET

conduction losses are high at low input voltages. The

maximum RDS(on) for the high-side MOSFET is:

EQUATION 6-3:

MAXIMUM

HIGH-SIDE RDS(ON)

For this design, where IRMS High-Side =3.9A at 12V

input voltage and 10A output current, the high-side

MOSFET should have a RDS(On) lower than 14 mΩ.

For the high-side MOSFET, most of the losses are

switching losses (70%). The maximum total gate

charge for the high-side MOSFET is:

EQUATION 6-4:

MAXIMUM TOTAL

GATE CHARGE FOR

THE HIGH-SIDE MOSFET

The maximum Total Gate Charge (QG(Total)) at 4.5V

VGS should be lower than 12 nC (calculated for 10A

output current).

OUT

OUTmax



Eff

------------------------------------------

LOSS

OUT

–

TABLE 6-3:

ESTIMATION OF THE POWER

LOSSES DISTRIBUTION

Component

Losses (%)

High-Side MOSFET

Low-Side MOSFET

Inductor

Input Capacitor

Output Capacitor

PWM Controller

Traces DC Resistance

DS on



LOSS High

Side

–

RMS High

Side

–

-----------------------------------------

0.3



GTotal



LOSS High

Side

–

IN Max



OUT



-------------------------------------------------------0.7



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