CS89712 datasheet(143/170 Pages) CIRRUS

143 / 170 page

CS89712

DS502PP2

143

IrDA and

RS232

Interfaces

LEDDRV

Infrared LED drive output (UART1)

PHDIN

Photo diode input (UART1)

TXD[1-2]

L4, G5

RS232 UART1 and 2 TX outputs

RXD[1-2]

M4, H3

RS232 UART1 and 2 RX inputs

DSR

RS232 DSR input

DCD

RS232 DCD input

CTS

RS232 CTS input

LCD

DD[0-3]

D3, C3,

B3, A3

I/O

LCD serial display data; pins can be used on power up to read

the ID of some LCD modules (See Figure 31).

CL[1]

LCD line clock

CL[2]

LCD pixel clock

FRM

LCD frame synchronization pulse output

LCD AC bias drive

Keyboard and

Buzzer drive

LED Flasher

COL[0-7]

Keyboard column drives (SYSCON1)

BUZ

Buzzer drive output (SYSCON1)

PD[0]/

LEDFLSH

LED flasher driver — multiplexed with Port D bit 0. This pin can pro-

vide up to 4 mA of drive current.

General

Purpose I/O

PA[0:7]

I/O

Port A I/O (bit 6 for boot clock option, bit 7 for CL-PS6700 PRDY

input); also used as keyboard row inputs

PB[0]/PRDY1

PB[1]/PRDY2

PB[2:7]

I/O

Port B I/O. All eight Port B bits can be used as GPIOs.

When the PC CARD1 or 2 control bits in the SYSCON2 register are

de-asserted, PB[0] and PB[1] are available for GPIO. When

asserted, these port bits are used as the PRDY signals for connected

CL-PS6700 PC Card Host Adapter devices.

PD[0:7]

I/O

Port D I/O

PE[0]/

BOOTSEL[0]

I/O

Port E I/O (3 bits only). Can be used as general purpose I/O during

normal operation.

PE[1]/

BOOTSEL[1]

I/O

During power-on reset, PE[0] and PE[1] are inputs and are latched by

the rising edge of nPOR to select the memory width that the CS89712

will use to read from the boot code storage device (i.e., external 8-bit-

wide FLASH bank).

PE[2]

I/O

During power-on reset, PE[2] is latched by the rising edge of nPOR to

enable the PLL clocking mode.

PWM

Drives

DRIVE[0:1]

L9, L7

I/O

PWM drive outputs. These pins are inputs on power up to determine

what polarity the output of the PWM should be when active. Other-

wise, these pins are always an output (See Table 91).

FB[0:1]

M9, P7

PWM feedback inputs

Boundary

Scan

TDI

JTAG data in

TDO

JTAG data out

TMS

JTAG mode select

TCLK

JTAG clock

nTRST

M15

JTAG async reset

Test

nTEST[0:1]

K6, J9

Test mode select inputs are used in conjunction with the power-on

latched state of nURESET to select the various device test modes.

Function

Signal

Name

Signal

Description

Table 90. External Signal Functions (Continued)

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