CS89712 datasheet(47/170 Pages) CIRRUS

47 / 170 page

CS89712

DS502PP2

2.25.3

LED Connection

Each LED output is capable of sinking 10 mA to

drive an LED directly through a series resistor. The

output voltage of each pin is less than 0.4 V when

the pin is low.

2.26 Media Access Control Engine

2.26.1

Overview

The CS89712’s Ethernet Media Access Control

(MAC) engine is fully compliant with the IEEE

802.3 Ethernet standard (ISO/IEC 8802-3, 1993). It

handles all aspects of Ethernet frame transmission

and reception, including: collision detection, pre-

amble generation and detection, and CRC genera-

tion and test. Programmable MAC features include

automatic retransmission on collision, and padding

of transmitted frames. The primary functions of the

MAC are: frame encapsulation and decapsulation;

error detection and handling; and, media access

management.

2.26.2

Frame Encapsulation/Decapsulation

The Ethernet port’s MAC engine automatically as-

sembles transmit packets and disassembles receive

packets. It also determines if transmit and receive

frames are of legal minimum size.

2.26.2.1

Transmission

Once the proper number of bytes have been trans-

ferred to the Ethernet port’s memory (either 5, 381,

1021 bytes, or full frame), and providing that ac-

cess to the network is permitted, the MAC automat-

ically transmits the 7-byte preamble (1010101b...),

followed by the Start-of-Frame Delimiter (SFD,

10101011b), and then the serialized frame data. It

then transmits the Frame Check Sequence (FCS).

The data after the SFD and before the FCS (Desti-

nation Address, Source Address, Length, and data

field) is supplied by the software. FCS generation

by the Ethernet port may be disabled by setting the

InhibitCRC bit (TxCMD register, bit C).

Figure 13 shows the Ethernet frame format.

2.26.2.2

Reception

The MAC receives the incoming packet as a serial

stream of NRZ data from the Manchester encod-

er/decoder. It begins by checking for the SFD.

Once the SFD is detected, the MAC assumes all

subsequent bits are frame data. It reads the DA and

compares it to the criteria programmed into the ad-

dress filter (see Section 2.32.7, “Receive Ethernet

Port Locations” for a description of Address Filter-

ing). If the DA passes the address filter, the frame

is loaded into the Ethernet port’s memory. If the

BufferCRC bit (RxCFG register, bit B) is set, the

received FCS is also loaded into memory. Once the

entire packet has been received, the MAC validates

the FCS. If an error is detected, the CRCerror bit

(RxEvent register, Bit C) is set.

1 byte

up to 7 bytes

6 bytes

2 bytes

LLC data

Pad

FCS

4 bytes

preamble

frame length

min 64 bytes

max 1518 bytes

alternating 1s / 0s

SFD

SFD = Start of Frame Delimiter

DA = Destination Address

SA = Source Address

Direction of Transmission

Frame

Packet

LLC = Logical Link Control

FCS = Frame Check Sequence (also

called Cyclic Redundancy Check, or CRC)

Length Field

Figure 13. Ethernet Frame Format

CS89712 датащи(PDF) 47 Page - Cirrus Logic

CS89712 датащи(HTML) 47 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL