CS89712 datasheet(73/170 Pages) CIRRUS

73 / 170 page

CS89712

DS502PP2

3.2.2

Ethernet Port Indexed Registers

Central to the Ethernet port architecture is a

4 Kbyte page of integrated RAM, which is used for

temporary storage of transmit and receive frames,

and for additional registers. These registers are ac-

cessed by use with the Ethernet Data Pointer and

Data Ports. These registers are organized into the

following sections:

3.2.2.1

Bus Interface Registers

The Bus Interface Registers contain Ethernet Port

interrupt enables, EEPROM control and data, and

receive frame information.

3.2.2.2

Status and Control Registers

The Status and Control registers are the primary

means of controlling and reading status of the

Ethernet port. They are detailed in Section 3.2.3,

“Ethernet Status/Control Registers”.

3.2.2.3

Initiate Transmit Registers

The TxCMD/TxLength registers are used to initiate

Ethernet frame transmission. These are detailed in

Section 3.19, “Initiate Transmit Registers”. (Also

see Section 2.34, “Transmit Operation” for a de-

scription of frame transmission.)

3.2.2.4

Address Filter Registers

The Filter registers store the Individual Address fil-

ter and Logical Address filter used by the Destina-

tion Address filter. These registers are described in

more detail in Section 3.20, “Address Filter Regis-

ters”. For a description of the DA filter, see Section

2.32.7, “Receive Ethernet Port Locations”.

3.2.2.5

Receive/Transmit Frame Locations

The Receive and Transmit Frame Ethernet Port lo-

cations are used to transfer Ethernet frames to and

from the host RAM. The software simply writes to

and reads from these locations and internal buffer

memory is dynamically allocated between transmit

and receive as needed. This provides more efficient

use of buffer memory and better overall network

performance. As a result of this dynamic alloca-

tion, only one receive frame and one transmit frame

are directly accessible.

3.2.3

Ethernet Status/Control Registers

The Status and Control registers are the primary

registers used to control and check the status of the

Ethernet port in the CS89712. They are organized

into two groups: Configuration/Control Registers

and Status/Event Registers. All Status and Control

Registers are 16-bit words as shown in Figure 23.

Bit 0 indicates whether it is a Configuration/Con-

trol Register (Bit 0 = 1) or a Status/Event Register

(Bit 0 = 0). Bits 0 through 5 provide an internal ad-

dress code that describes the exact function of the

tion/Control and Status/Event bits.

3.2.4

Configuration and Control Registers

Configuration and Control registers are used to set-

up the following:

•

how frames will be transmitted and received;

•

which frames will be transmitted and received;

•

which events will cause interrupts to the pro-

cessor; and,

•

Configuration of the Ethernet physical interface.

These registers are read/write and are designated

by odd numbers (e.g. Register 1, Register 3, etc.).

The Transmit Command Register (TxCMD) is a

special type of register. It appears in two separate

locations in the Ethernet Port memory map. The

first location, Ethernet Port offset address 0108h, is

within the block of Configuration/Control Regis-

ters and is read-only. The second location, Ethernet

Port offset address 0144h, is where the actual trans-

mit commands are issued and is write-only. See

Section 3.2.7, “Status/Control Register Summary”

and Section 2.34, “Transmit Operation” for a more

detailed description of the TxCMD register.

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