CS89712 datasheet(142/170 Pages) CIRRUS

142 / 170 page

CS89712

142

DS502PP2

Power

Management

nPWRFL

Power fail input; active low, deglitched input to force system into the

Standby State (Note 1)

BATOK

L14

Main battery OK input; falling edge generates a FIQ, a low level in the

Standby State inhibits system start up; deglitched input (Note 2)

nEXTPWR

M13

External power sense; must be driven low if the system is powered by

an external source

nBATCHG

K13

New battery sense; driven low if battery voltage falls below the "no-

battery" threshold; it is a deglitched input (Note 2)

State Control

nPOR

M16

Power-on reset input. This signal is not deglitched. When active it

completely resets the entire system, including all the RTC registers.

Upon power-up, the signal must be held active low for a minimum of

100

µsec after V

DD has settled. During normal operation, nPOR

needs to be held low for at least one clock cycle of the selected clock

speed (i.e., when running at 74 MHz, the pulse width of nPOR needs

to be > 14 nsec).

Note that nURESET, TEST(0), TEST(1), PE(0), PE(1), PE(2),

DRIVE(0), DRIVE(1), DD(0), DD(1), DD(2), and DD(3) are all latched

on the rising edge of nPOR.

RUN

This pin is the RUN signal. The pin will be high when the system is

active or idle, low while in the Standby State. See Table 91.

WAKEUP

F10

Wake up is a deglitched input signal. It must be held high for at least

125

µsec to guarantee its detection. Once detected it forces the sys-

tem into the Operating State from the Standby State. It is only active

when the system is in the Standby State. This pin is ignored when the

system is in the Idle or Operating State. It is used to wakeup the sys-

tem after first power-up, or after software has forced the system into

the Standby State. WAKEUP will be ignored for up to two seconds

after nPOR goes HIGH. Therefore, the external WAKEUP logic must

be designed to allow it to rise and stay HIGH for at least 125 usec,

two seconds after nPOR goes HIGH. (Note 2)

nURESET

H12

User reset input; active low deglitched input from user reset button.

This pin is also latched upon the rising edge of nPOR and read along

with the input pins nTEST[0-1] to force the device into special test

modes. nURESET does not reset the RTC. (Note 2)

DAI, Codec or

SSI2

Interface

(SeeTable 22 )

SSICLK

I/O

DAI/Codec/SSI2 clock signal

SSITXFR

I/O

DAI/Codec/SSI2 serial data output frame/synchronization pulse out-

put

SSITXDA

K10

DAI/Codec/SSI2 serial data output

SSIRXDA

DAI/Codec/SSI2 serial data input

SSIRXFR

I/O

SSI2 serial data input frame/synchronization pulse

DAI external clock input

ADC

Interface

(SSI1)

ADCCLK

Serial clock output

nADCCS

Chip select for ADC interface

ADCOUT

Serial data output

ADCIN

Serial data input

SMPCLK

Sample clock output

Function

Signal

Name

Signal

Description

Table 90. External Signal Functions (Continued)

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