CS89712 datasheet(134/170 Pages) CIRRUS

134 / 170 page

CS89712

134

DS502PP2

CS89712 does not transmit a frame if TxLength is less than 3. See Section 2.34,

“Transmit Operation”.

Since this register is write-only, its initial state after reset is undefined.

3.19.2

Transmit Length (TxLength, address offset 146h)

This register is used in conjunction with the TxCMD register. When a transmission is initiated via a command in Tx-

CMD, the length of the transmitted frame is written into this register. The length of the transmitted frame may be

modified by the configuration of the TxPadDis and InhibitCRC bits in the TxCMD register. See Table 30, and Section

2.34,

“Transmit Operation”. TxLength must be >3 and < 1519.

Since this register is write-only, its initial state after reset is undefined.

3.20 Address Filter Registers

3.20.1

Logical Address Filter (hash table, address offset 0150h)

The CS89712 hashing decoder circuitry compares its output with one bit of the Logical Address Filter Register. If

the decoder output and the Logical Address Filter bit match, the frame passes the hash filter and the Hashed bit

Bit

Description

001001: These bits provide an internal address used to identify this as register 9. When read-

ing this register, these bits will be 001001, where the LSB corresponds to Bit 0.

TxStart: This pair of bits determines how many bytes are transferred to the CS89712 before

the MAC starts the packet transmit process.

Force: When set in conjunction with a new transmit command, any transmit frames waiting in

the transmit buffer are deleted. If a previous packet has started transmission, that packet is ter-

minated within 64 bit times with a bad CRC.

Onecoll: When this bit is set, any transmission will be terminated after only one collision. When

clear, the CS89712 allows up to 16 normal collisions before terminating the transmission.

InhibitCRC: When set, the CRC is not appended to the transmission.

TxPadDis: When TxPadDis is clear, if the software gives a transmit length less than 60 bytes

and InhibitCRC is set, then the Ethernet port pads to 60 bytes. If the software gives a transmit

length less than 60 bytes and InhibitCRC is clear, then the CS89712 pads to 60 bytes and

appends the CRC.

When TxPadDis is set, the CS89712 allows the transmission of runt frames (a frame less than

64 bytes). If InhibitCRC is clear, the CS89712 appends the CRC. If InhibitCRC is set, the

CS89712 does not append the CRC.

Table 84. Transmit Command

Address 0147h

Address 0146h

Most-significant byte of Transmit Frame Length

Least-significant byte of Transmit Frame Length

Bit 7

Bit 6

Start transmission after 5 bytes are in the CS89712

Start transmission after 381 bytes are in the CS89712

Start transmission after 1021 bytes are in the CS89712

Start transmission after the entire frame is in the CS89712

Address 0157h Address 0156h Address 0155h Address 0154h Address 0153h Address 0152h Address 0151h Address 0150h

Most-signifi-

cant byte of

hash filter.

Least-signifi-

cant byte of

hash filter.

CS89712 датащи(PDF) 134 Page - Cirrus Logic

CS89712 датащи(HTML) 134 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL