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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS89712 датащи(PDF) 131 Page - Cirrus Logic |
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CS89712 датащи(HTML) 131 Page - Cirrus Logic |
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131 / 170 page  CS89712 DS502PP2 131 3.18.16 Ethernet IRQ Control Register (BusCTL, address offset 116h) After reset, if no EEPROM is found by the CS89712, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the EE- PROM”. Reset value is: 0000 0000 0001 0111 76 5:0 F E D:8 RSVD 010111 EnableIRQ RSVD Bit Description 5:0 010111: These bits provide an internal address used by the CS89712 to identify this as register 17, the Bus Control Register. 6 D:8 RSVD: Reserved; must be a “0” when writing to this register. F EnableIRQ: When set, the CS89712 will generate an interrupt in response to an interrupt event (Section 2.31, “Managing Interrupts & Status Queue”). When cleared, the CS89712 will not generate any interrupts. Table 81. Ethernet IRQ Control |
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