CS89712 datasheet(137/170 Pages) CIRRUS

137 / 170 page

CS89712

DS502PP2

137

4.1.3

Debug / ICE Test Mode

This mode is selected by nTEST0 = 0, nTEST1 =

0, Latched nURESET = 1.

Selection of this mode enables the debug mode of

the ARM720T. By default, this is disabled which

saves approximately 3% on power.

4.1.4

Hi-Z (System) Test Mode

This mode selected by nTEST0 = 0, nTEST1 = 0,

Latched nURESET = 0.

This test mode asynchronously disables all output

buffers on the CS89712. This has the effect of re-

moving the CS89712 from the PCB so that other

devices on the PCB can be in-circuit tested. The in-

ternal state of the CS89712 is not altered directly

by this test mode.

4.1.5

Software Selectable Test Function-

ality

When bit 11 of the SYSCON register is set high, in-

ternal peripheral bus register accesses are output on

the main address and data buses as though they

were external accesses to the address space ad-

dressed by nCS[5]. Hence, nCS[5] takes on a dual

role, it will be active as the strobe for internal ac-

cesses and for any accesses to the standard address

range for nCS[5]. Additionally, in this mode, the

internal signals shown in Table 87 are multiplexed

out of the device on port pins.

This test is not intended to be used when LCD

DMA accesses are enabled. This is due to the fact

that it is possible to have internal peripheral bus ac-

tivity simultaneously with a DMA transfer. This

would cause bus contention to occur on the external

bus.

The “Waited clock to CPU” is an internally ANDed

source that generates the actual CPU clock. Thus, it

is possible to know exactly when the CPU is being

clocked by viewing this pin. The signals nFIQ and

nIRQ are the two output signals from the internal

interrupt controller. They are input directly into the

ARM720T processor.

Signal

I/O

Function

TSEL *

PA5

PLL test mode

XTLON *

PA4

Enable to oscillator circuit

PLLON *

PA3

Enable to PLL circuit

PLLBP

PA0

Bypasses PLL

RTCCLK

COL0

Output of RTC oscillator

CLK1

COL1

1 Hz clock from RTC divider chain

OSC36

COL2

36 MHz divided PLL main clock

CLK576K

COL4

576 KHz divided from above

VREF

COL6

Test clock output for PLL

Table 86. Oscillator and PLL Test Mode Signals

Signal

I/O

Function

CLK

PE0

Waited clock to CPU

nFIQ

PE1

nFIQ interrupt to CPU

nIRQ

PE2

nIRQ interrupt to CPU

Table 87. Software Selectable Test Functionality

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