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PSOC4100M датащи(PDF) 15 Page - Cypress Semiconductor |
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PSOC4100M датащи(HTML) 15 Page - Cypress Semiconductor |
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15 / 41 page ![]() PSoC® 4: PSoC 4100M Family Datasheet Document Number: 001-96519 Rev. *E Page 15 of 41 Electrical Specifications Absolute Maximum Ratings Device Level Specifications All specifications are valid for –40 °C TA 105 °C and TJ 125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Note 1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Table 1. Absolute Maximum Ratings[1] Spec ID# Parameter Description Min Typ Max Units Details/Conditions SID1 VDD_ABS Analog or digital supply relative to VSS (VSSD = VSSA) –0.5 – 6 V Absolute maximum SID2 VCCD_ABS Direct digital core voltage input relative to VSSD –0.5 – 1.95 V Absolute maximum SID3 VGPIO_ABS GPIO voltage; VDDD or VDDA –0.5 – VDD+0.5 V Absolute maximum SID4 IGPIO_ABS Current per GPIO –25 – 25 mA Absolute maximum SID5 IG-PIO_injection GPIO injection current per pin –0.5 – 0.5 mA Absolute maximum BID44 ESD_HBM Electrostatic discharge human body model 2200 – – V BID45 ESD_CDM Electrostatic discharge charged device model 500 – – V BID46 LU Pin current for latch-up –140 – 140 mA Table 2. DC Specifications Spec ID# Parameter Description Min Typ Max Units Details / Conditions SID53 VDD Power Supply Input Voltage (VDDA = VDDD = VDD) 1.8 – 5.5 V With regulator enabled SID255 VDDD Power Supply Input Voltage unregulated 1.71 1.8 1.89 V Internally unregulated Supply SID54 VCCD Output voltage (for core logic) – 1.8 – V SID55 CEFC External Regulator voltage bypass 1 1.3 1.6 µF X5R ceramic or better SID56 CEXC Power supply decoupling capacitor – 1 – µF X5R ceramic or better Active Mode, VDD = 1.71 V to 5.5 V, –40 °C to +105 °C SID6 IDD1 Execute from Flash; CPU at 6 MHz – 2.2 2.8 mA SID7 IDD2 Execute from Flash; CPU at 12 MHz – 3.7 4.2 mA SID8 IDD3 Execute from Flash; CPU at 24 MHz – 6.7 7.2 mA Sleep Mode, –40 °C to +105 °C SID21 IDD16 I2C wakeup, WDT, and Comparators on. Regulator Off. – 1.75 2.1 mA VDD = 1.71 to 1.89, 6MHz SID22 IDD17 I2C wakeup, WDT, and Comparators on. – 1.7 2.1 mA VDD = 1.8 to 5.5, 6 MHz SID23 IDD18 I2C wakeup, WDT, and Comparators on. Regulator Off. – 2.35 2.8 mA VDD = 1.71 to 1.89, 12 MHz SID24 IDD19 I2C wakeup, WDT, and Comparators on. – 2.25 2.8 mA VDD = 1.8 to 5.5, 12 MHz |
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