PSOC4100M datasheet(5/41 Pages) CYPRESS

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PSoC® 4: PSoC 4100M Family

Datasheet

Document Number: 001-96519 Rev. *E

Page 5 of 41

Functional Definition

CPU and Memory Subsystem

CPU

The Cortex-M0 CPU in the PSoC 4100-M is part of the 32-bit

MCU subsystem, which is optimized for low-power operation

with extensive clock gating. Most instructions are 16 bits in length

and execute a subset of the Thumb-2 instruction set. The

Cypress implementation includes a hardware multiplier that

provides a 32-bit result in one cycle. It includes a nested vectored

interrupt controller (NVIC) block with 32 interrupt inputs and also

includes a Wakeup Interrupt Controller (WIC), which can wake

the processor up from the Deep Sleep mode allowing power to

be switched off to the main processor when the chip is in the

Deep Sleep mode. The Cortex-M0 CPU provides a

Non-Maskable Interrupt (NMI) input, which is made available to

the user when it is not in use for system functions requested by

the user.

The CPU also includes a debug interface, the serial wire debug

(SWD) interface, which is a 2-wire form of JTAG; the debug

configuration used for PSoC 4100-M has four break-point

(address) comparators and two watchpoint (data) comparators.

Flash

The PSoC 4100-M has a flash module with a flash accelerator,

tightly coupled to the CPU to improve average access times from

the flash block. The flash accelerator delivers 85% of

single-cycle SRAM access performance on average. Part of the

flash module can be used to emulate EEPROM operation if

required.

SRAM

SRAM memory is retained during Hibernate.

SROM

A supervisory ROM that contains boot and configuration routines

is provided.

DMA

A DMA engine, with eight channels, is provided that can do 32-bit

transfers and has chainable ping-pong descriptors.

System Resources

Power System

The power system is described in detail in the section Power on

page 13. It provides assurance that voltage levels are as

required for each respective mode and either delay mode entry

(on power-on reset (POR), for example) until voltage levels are

as required for proper function or generate resets (brown-out

detect (BOD)) or interrupts (low voltage detect (LVD)). The

PSoC 4100M operates with a single external supply over the

range of 1.71 to 5.5 V and has five different power modes, transi-

tions between which are managed by the power system. The

PSoC 4100M provides Sleep, Deep Sleep, Hibernate, and Stop

low-power modes.

Clock System

The PSoC 4100-M clock system is responsible for providing

clocks to all subsystems that require clocks and for switching

between different clock sources without glitching. In addition, the

clock system ensures that no meta-stable conditions occur.

The clock system for the PSoC 4100-M consists of a Watch

Crystal Oscillator (WCO) running at 32 kHz, the IMO (3 to

48 MHz) and the ILO (32-kHz nominal) internal oscillators, and

provision for an external clock.

Figure 2. PSoC 4100M MCU Clocking Architecture

The clk_hf signal can be divided down to generate synchronous

clocks for the analog and digital peripherals. There are a total of

16 clock dividers for the PSoC 4100-M, each with 16-bit divide

capability. The analog clock leads the digital clocks to allow

analog events to occur before digital clock-related noise is

generated. The 16-bit capability allows a lot of flexibility in gener-

ating fine-grained frequency values and is fully supported in

PSoC Creator.

IMO Clock Source

The IMO is the primary source of internal clocking in the

PSoC 4100M. It is trimmed during testing to achieve the

specified accuracy. Trim values are stored in nonvolatile

memory. Trimming can also be done on the fly to allow in-field

calibration. The IMO default frequency is 24 MHz and it can be

adjusted between 3 to 48 MHz in steps of 1 MHz. IMO tolerance

with Cypress-provided calibration settings is ±2%.

ILO Clock Source

The ILO is a very low power oscillator, nominally 32 kHz, which

is primarily used to generate clocks for peripheral operation in

Deep Sleep mode. ILO-driven counters can be calibrated to the

IMO to improve accuracy. Cypress provides a software

component, which does the calibration.

Crystal Oscillator

The PSoC 4100M clock subsystem also includes a

low-frequency crystal oscillator (32-kHz WCO) that is available

during the Deep Sleep mode and can be used for Real-Time

Clock (RTC) and Watchdog Timer applications.

dsi_out[3:0]

IMO

WCO

ILO

clk_ext

clk_hf

clk_lf

dsi_in[3]

dsi_in[2]

dsi_in[0]

dsi_in[1]

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