CS8415A-CS datasheet(30/42 Pages) CIRRUS

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CS8415A

10. HARDWARE MODE

The CS8415A has a hardware mode which allows

using the device without a microcontroller. Hard-

ware mode is selected by connecting the H/S pin

to VL+. Various pins change function in hardware

mode, described in the hardware mode pin defini-

tion section.

Hardware mode data flow is shown in Figure 9. Au-

dio data is input through the AES3 receiver, and

routed to the serial audio output port. The PRO,

COPY, ORIG, EMPH, and AUDIO channel status

bits are output on pins. The decoded C and U bits

are also output, clocked at both edges of OLRCK

(master mode only, see Figure 7).The current au-

dio sample is passed unmodified to the serial audio

output port if the validity bit is high, or a parity, bi-

phase, or PLL lock error occurs.

10.1

Serial Audio Port Formats

In hardware mode, only a limited number of alter-

native serial audio port formats are available.

Table 2 defines the equivalent software mode bit

settings for each format.

Start-up options are

shown in Table 3, and allow choice of the serial au-

dio output port as a master or slave, and the serial

audio port format.

SOSF

SORES1/0

SOJUST

SODEL

SOSPOL

SOLRPOL

OF1 - Left Justified

OF2 - I2S 24-bit data

010

OF3 - Right Justified, master mode only

OF4 - Direct AES3 data

Table 2. Equivalent Software Mode Bit Definitions

SDOUT

ORIG

EMPH

Function

Serial Output Port is Slave

Serial Output Port is Master

Left Justified

I2S 24-bit data

Right Justified

Direct AES3 data

Table 3. Hardware Mode Start-up Options

Serial

Audio

O utput

AES3 Rx

Decoder

C & U bit Data Buffer

RXP

RXN

OLRCK

OSCLK

SDO UT

RM CK

RERR

COPY ORIG

EM PH

RCBL

PRO AUDIO

CHS

H/S

Power supply pins (VD+, VA+, DGN D, AGN D) & the reset pin (RST) and the PLL filter pin (FILT)

are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.

VL +

NVERR

Figure 9. Hardware Mode

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