CS8415A

22

SDOUT pin only, serial audio output port clock must be derived from the AES3 receiver recov-

ered clock)

SOJUST - Justification of SDOUT data relative to OLRCK

Default = ‘0’

0 - Left-justified

1 - Right-justified (master mode only)

SODEL - Delay of SDOUT data relative to OLRCK, for left-justified data formats

Default = ‘0’

0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge

1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge

SOSPOL - OSCLK clock polarity

Default = ‘0’

0 - SDOUT sampled on rising edges of OSCLK

1 - SDOUT sampled on falling edges of OSCLK

SOLRPOL - OLRCK clock polarity

Default = ‘0’

0 - SDOUT data is for the left channel when OLRCK is high

1 - SDOUT data is for the right channel when OLRCK is high

8.5

Interrupt 1 Status (07h) (Read Only)

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register

was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register.

Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true.

Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults

to 00h.

OSLIP - Serial audio output port data slip interrupt

When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port

data source, This bit will go high every time a data sample is dropped or repeated.

DETC - D to E C-buffer transfer interrupt.

The source for this bit is true during the D to E buffer transfer in the C bit buffer management

process.

RERR - A receiver error has occurred.

The Receiver Error register may be read to determine the nature of the error which caused the

interrupt.

7

6

5

4

32

10

0

OSLIP

0

0

0

DETC

0

RERR