CS8415A-CS datasheet(14/42 Pages) CIRRUS

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CS8415A

5. AES3 RECEIVER

The CS8415A includes an AES3 digital audio re-

ceiver. A comprehensive buffering scheme pro-

vides read access to the channel status and user

data. This buffering scheme is described in Appen-

dix B.

The AES3 receiver accepts and decodes audio

and digital data according to the AES3, IEC60958

(S/PDIF), and EIAJ CP-1201 interface standards.

The receiver consists of a differential input stage,

driven through pins RXP0 and RXN0, a PLL based

clock recovery circuit, and a decoder which sepa-

rates the audio data from the channel status and

user data.

External components are used to terminate and

isolate

the

incoming

data

cables

from

the

CS8415A. These components are detailed in Ap-

pendix A.

5.1

7:1 S/PDIF Input Multiplexer

The CS8415A employs a 7:1 S/PDIF Input Multi-

plexer to accommodate up to seven channels of in-

put digital audio data. Digital audio data is single-

ended and input through the RXP0-6 pins. When

any portion of the multiplexer is implemented, un-

used RXP pins should be tied to ground, and

RXN0 must be ac-coupled to ground. The multi-

plexer select line control is accessed through bits

MUX2:0 in the Control 2 register. The multiplexer

defaults to RXP0. Therefore, the default configura-

tion is for a differential signal to be input through

RXP0 & RXN0. Please see Appendix A for recom-

mended input circuits.

5.2

OMCK System Clock Mode

A special clock switching mode is available that al-

lows the clock that is input through the OMCK pin

to be output through the RMCK pin. This feature is

controlled by the SWCLK bit in register 1 of the

control registers. When the PLL loses lock, the fre-

quency of the VCO drops to 300 kHz. The clock

switching mode allows the clock input through

OMCK to be used as a clock in the system without

any disruption when the PLL loses lock, for exam-

ple, when the input is removed from the receiver.

When SWCLK is enabled and this mode is imple-

mented, RMCK is an output and is not bi-direction-

al. This clock switching is done glitch free. Please

note that internal circuitry associated with RMCK is

not driven by OMCK. This means that OSCLK and

OLRCK continue to be derived from the PLL and

are not usable in this mode. This function is avail-

able only in software mode.

5.3

PLL, Jitter Attenuation, and

Varispeed

Please see Appendix C for general description of

the PLL, selection of recommended PLL filter com-

ponents, and layout considerations. Figure 5

shows the recommended configuration of the two

capacitors and one resistor that comprise the PLL

filter.

5.4

Error Reporting and Hold Function

While decoding the incoming AES3 data stream,

the CS8415A can identify several kinds of error, in-

dicated in the Receiver Error register. The UN-

LOCK bit indicates whether the PLL is locked to

the incoming AES3 data. The V bit reflects the cur-

rent validity bit status. The CONF (confidence) bit

is the logical OR of BIP and UNLOCK. The BIP (bi-

phase) error bit indicates an error in incoming bi-

phase coding. The PAR (parity) bit indicates a re-

ceived parity error.

The error bits are "sticky": they are set on the first

occurrence of the associated error and will remain

set until the user reads the register through the

control port. This enables the register to log all un-

masked errors that occurred since the last time the

The Receiver Error Mask register allows masking

of individual errors. The bits in this register serve

as masks for the corresponding bits of the Receiv-

er Error Register. If a mask bit is set to 1, the error

is unmasked, which implies the following: its occur-

rence will be reported in the receiver error register,

induce a pulse on RERR, invoke the occurrence of

a RERR interrupt, and affect the current audio

sample according to the status of the HOLD bits.

The HOLD bits allow a choice of holding the previ-

ous sample, replacing the current sample with zero

(mute), or not changing the current audio sample.

If a mask bit is set to 0, the error is masked, which

implies the following: its occurrence will not be re-

ported in the receiver error register, will not induce

a pulse on RERR or generate a RERR interrupt,

and will not affect the current audio sample. The

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