MIC24045 datasheet(17/46 Pages) MICROCHIP

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 2016 Microchip Technology Inc.

DS20005568A-page 17

MIC24045

3.8

I2C Clock Input Pin (SCL)

The SCL pin is the serial interfaces Serial Clock

pin.This pin is connected to the Host Controllers SCL

pin.

The MIC24045 is a slave device, so its SCL pin accepts

only external clock signals.

3.9

I2C Data Input/Output Pin (SDA)

The SDA pin is the serial interface Serial Data pin. This

pin is connected to the Host Controllers SDA pin. The

SDA pin has an open-drain N-channel driver.

3.10

Analog Ground Pin (AGND)

This pin is a quiet ground for the analog circuitry of the

internal regulator and a return terminal for the external

compensation network.

3.11

Transconductance Error Amplifier

Output Pin (COMP)

Connect a compensation network from this pin to

AGND.

3.12

Output Sensing Pin (OUTSNS)

Connect this pin directly to the buck converter output

voltage. This pin is the top side terminal of the internal

feedback divider.

3.13

Precision Enable Input Pin (EN)

The EN pin is compared to a 1.21V typical threshold to

determine the turn-on of the device. After reaching the

turn-on threshold, the I2C-programmable turn-on delay

counter starts. A 2 µA (typical) current source pulls

down the EN pin to prevent unwanted power delivery in

case of a floating EN input. A 135 mV typical hysteresis

prevents chattering when power delivery is started.

3.14

Internal Regulator Output Pin

(VDDA)

Output of the internal linear regulator and internal sup-

ply for analog control. A 1 µF minimum ceramic capac-

itor should be connected from this pin to AGND; a 2.2 µF

typical value is recommended.

3.15

MOSFET Drivers Internal Supply

Pin (VDDP)

Internal supply rail for the MOSFET drivers, fed by the

VDDA pin. An internal resistor (10) between the VDDP

and VDDA pins is provided in the regulator in order to

implement an RC filter for switching noise suppression.

A 1 µF minimum ceramic capacitor should be

connected from this pin to PGND; a 2.2 µF typical value

is recommended.

3.16

Internal Regulator Input Pin

(VINLDO)

This pin is typically connected to the input voltage of the

buck converter stage (VIN). If VINLDO and VIN are

connected to different voltage rails, individually bypass

VINLDO to ground with a 100 nF ceramic capacitor.

3.17

PGND Exposed Pad (PGND_EP)

Electrically connected to PGND pins. Connect with

thermal vias to the ground plane to ensure adequate

heat-sinking.

See

Section 9.0

“Packaging

Information”

3.18

VIN Exposed Pad (VIN_EX)

Electrically connected to VIN pins. If an input power dis-

tribution plane is available, connect with thermal vias to

that plane to improve heat-sinking. See Section 9.0

“Packaging Information”

3.19

LX Exposed Pad (LX_EP)

Electrically connected to LX pins. See Section 9.0

“Packaging Information”

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