MIC24045 datasheet(32/46 Pages) MICROCHIP

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MIC24045

DS20005568A-page 32

 2016 Microchip Technology Inc.

The overall voltage loop gain TV(S) is the product of the

control-to-output

and

the

compensator

transfer

functions:

EQUATION 7-15:

The value of the attenuation ratio R1/(R1 + R2)

depends on the output voltage selection and can be

retrieved as illustrated in Table 7-2:

The compensation design process is as follows:

Set the TV(S) loop gain crossover frequency fXO

in the range fS/20 to fS/10. Lower values of fXO

allow a more predictable and robust phase mar-

gin. Higher values of fXO would involve addi-

tional considerations about the current loop

bandwidth in order to achieve a robust phase

margin. Taking a more conservative approach is

highly recommended.

EQUATION 7-16:

Select RC1 to achieve the target crossover fre-

quency fXO of the overall voltage loop. This typ-

ically happens where the power stage transfer

function GCO(S) is rolling off at -20 dB/dec. The

compensator transfer function HC(S) is in the

so-called mid-band gain region where CC1 can

be considered a DC-blocking short circuit while

CC2 can still be considered as an open circuit, as

calculated in Equation 7-17:

EQUATION 7-17:

Select capacitor CC1 to place the compensator

zero at the load pole. The load pole moves

around with load variations, so, to calculate the

load pole, use as a load resistance RL the equiv-

alent value that yields the nominal output current

IOUT of the application at the output voltage

VOUT, as shown in: Equation 7-18 and

Equation 7-19:

EQUATION 7-18:

EQUATION 7-19:

Select capacitor CC2 to place the compensator

pole at the output capacitor ESR zero frequency

fZ, or at  5fXO, whichever is lower.

The CC2 is intended for placing the compensator pole

at the frequency of the output capacitor ESR zero,

and/or achieve additional switching ripple/noise

attenuation.

If the output capacitor is a polarized one, its ESR zero

will typically occur at low enough frequencies to cause

the loop gain to flatten out and not roll-off at a

-20 dB/decade slope around, or just after the crossover

frequency fXO. This causes undesirable scarce

compensation design robustness and switching noise

susceptibility. The compensator pole is then used to

cancel the output capacitor ESR zero and achieve a

well-behaved roll-off of the loop gain above the

crossover frequency.

If the output capacitors are only ceramic, then the ESR

zeroes frequencies could be very high. In many cases,

the frequencies could even be above the switching fre-

quency itself. Loop gain roll-off at -20 dB/decade well

beyond the crossover frequency is ensured, but even in

this case, it is good practice to still make use of the

compensator pole to further attenuate switching noise,

while conserving phase margin at the crossover fre-

quency. For example, setting the compensator pole at

5 fXO, will limit its associated phase loss at the cross-

over frequency to about 11°. Placement at even higher

frequencies N × fXO (N > 5) will reduce phase loss even

further, at the expense of less noise/ripple attenuation

at the switching frequency. Some attenuation of the

switching frequency noise/ripple is achieved as long as

N× fXO < fS.

TABLE 7-2:

INTERNAL FEEDBACK

DIVIDER ATTENUATION

VALUES

VOUT Range

R1/(R1 + R2)

(A =1 +R2/R1)

0.640V – 1.280V

1.290V – 1.950V

0.5

1.980V – 3.420V

0.333

4.750V – 5.250V

0.2



CO S





------



---------------------



 2 COUT



------------------------------------------



OUT

-------------

OUT

ESR





--------------------------------------------------

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