MIC24045 datasheet(35/46 Pages) MICROCHIP

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DS20005568A-page 35

MIC24045

8.3

Device Address

The MIC24045 device uses a 7-bit address, which is

set in hardware, using three-state pins ADR0 and

ADR1 (HIGH, LOW, or high-Z). These two three-state

pins allow for nine different addresses, as described in

Table 8-1 below.

8.4

Acknowledge

The number of data bytes transferred between the

START and the STOP conditions, from transmitter to

receiver, is not limited. Each byte of eight bits is fol-

lowed by one Acknowledge bit. The Acknowledge bit is

a HIGH level put on the bus by the transmitter, whereas

the master generates an extra acknowledge-related

clock pulse. The device that acknowledges has to pull

down the SDA line during the acknowledge clock pulse,

so that the SDA line is stable LOW during the HIGH

period of the acknowledge-related clock pulse; setup

and hold times must be taken into account.

A slave receiver which is addressed must generate an

acknowledge after the reception of each byte.

Also, a master receiver must generate an acknowledge

after the reception of each byte that has been clocked

out of the slave transmitter, except on the last received

byte. A master receiver must signal an end of data to

the transmitter by not generating an acknowledge on

the last byte that has been clocked out of the slave

transmitter. In this event, the transmitter must leave the

data line HIGH to enable the master to generate a

STOP condition.

8.5

Bus transactions

8.5.1

SINGLE WRITE

The first seven bits of the first byte make up the slave

address. The eighth bit is the LSB (Least Significant

bit). It determines the direction of the message (R/W).

A ‘zero’ in the least significant position of the first byte

means that the master will write information to a

selected slave. A ‘1’ in this position means that the

master will read information from the slave. When an

address is sent, each device in a system compares the

first seven bits after the START condition with its

address. If they match, the device considers itself

addressed by the master as a slave-receiver or

slave-transmitter, depending on the R/W bit.

Command byte is a data byte which selects a register

on the device. The Least Significant six bits of the com-

mand byte determine the address of the register that

needs to be written.

The data to port is the 8-bit data that needs to be written

to the selected register. This is followed by the

acknowledge from the slave and then the STOP condi-

tion.

The Write command is as follows and it is illustrated in

the timing diagram below:

Send START sequence

Send 7-bit slave address

Send the R/W bit - 0 to indicate a write operation

Wait for acknowledge from the slave

Send the command byte – address that needs to

be written

Wait for acknowledge from the slave

Receive the 8-bit data from the master and write

it to the slave register indicated in step 5 starting

from MSB

Acknowledge from the slave

Send STOP sequence

FIGURE 8-3:

Single Write Timing Diagram.

TABLE 8-1:

MIC24045 I2C ADDRESS

SETTING

ADR1

ADR0

I2C Address

101 0000

101 0001

101 0010

101 0011

high-Z

101 0100

high-Z

101 0101

high-Z

101 0110

high-Z

101 0111

high-Z

101 1000

SDA

SCL

DATA 1

START condition

R/W ACK from

Slave

Slave address

Command byte

ACK from

Slave

ACK from

Slave

Data to port

Data out from port

DATA 1 VALID

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