COM20022I datasheet(77/83 Pages) SMSC

77 / 83 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

SMSC COM20022I

Page 77

Rev. 08-18-03

DATASHEET

Table 8.1 - DMA Timing

PARAMETER

MIN

TYP

MAX

UNIT

NOTE

nDACK Inactive Pulse Width

The First DREQ Assertion Delay After Writing Low

Pointer

4 Tarb

Tarb

5Tarb

+40ns

Note 1

DREQ Assert Delay from nREFEX Active at

Programmable Burst Transfer Mode

Note 3

DREQ Assertion Delay from Write/Read Inactive at Non-

Burst Transfer Mode

Note 4

GTTM

bit =0

7Txtl

8Txtl

+40ns

Note 2

DREQ Assertion Delay from nDACK

Inactive due to Timeout of Gate Timer

at Programmable Burst Transfer Mode

GTTM bit=1

15Txtl

16Txtl

+40ns

DREQ Negation Delay from Write/Read Active

Note 4

DREQ Negation Delay from TC and Write/Read Active

Note 4

Data Access Time from Read Active

Note 4

Data Float Delay from Read Inactive

Note 4

t10

nREFEX Active Pulse Width

t11

Write Active Pulse Width

CASE 1W

Note

4,5

CASE 2W

t12

Read Active Pulse Width

CASE 1R

Note

4,5

CASE 2R

100

t13

Active Pulse Overlap Width between TC and Write/Read

Note 4

CASE1w/1R

t14

Write/Read Inactive Pulse Width

CASE2w/2R

Note

4,5

t15

Write Cycle Interval Period

4Tarb

Note

1,4

CASE1R

4Tarb

t16

Read Cycle Interval Period

CASE2R

4Tarb+3

0nS

Note

1,4,5

t17

Data Setup to Write Inactive

Note 4

t18

Data Hold From Write Inactive

Note 4

t19

nCS High Setup to nDACK Active

t20

nCS High Hold from nDACK Inactive

t21

DREQ Active Setup to nDACK Active

t22

DIR Setup to nDS Low (Motorola mode only)

t23

DIR Hold from nDS High (Motorola mode only)

t24

nDACK Setup to Write/Read Active

Note 4

t25

nDACK Hold After Write/Read Inactive

Note 4

t26

nREFEX Inactive Time

3Txtl

Note 2

Notes:

Tarb is the ARBITRATION CLOCK PERIOD. It depends on Topr and SLOWARB bit.

SLOWARB must set to “1” if the data rate is over 5 Mbps. (i.e. 10 Mbps)

Tarb is Topr at SLOWARB=0 and Tarb is 2Topr at SLOWARB=1.

Topr is the period of Operation Clock Frequency. It depends on the CKUP1 and CKUP0 bits.

Txtl is a period of external XTAL oscillation frequency.

The nREFEX pin must not be Low while nDACK is Low.

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