COM20022I datasheet(4/83 Pages) SMSC

4 / 83 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

Rev. 08-18-03

Page 4

SMSC COM20022I

DATASHEET

Table of Contents

Revision History .......................................................................................................................................... 3

Chapter 1

General Description................................................................................................................ 7

Chapter 2

Pin Configuration.................................................................................................................... 8

Chapter 3

Description of Pin Functions .................................................................................................. 9

Chapter 4

Protocol Description ............................................................................................................. 12

4.1

Network Protocol........................................................................................................................................12

4.2

Data Rates .................................................................................................................................................12

4.2.1

Selecting Clock Frequencies Above 2.5 Mbps....................................................................................13

4.3

Network Reconfiguration ............................................................................................................................13

4.4

Broadcast Messages..................................................................................................................................14

4.5

Extended Timeout Function .......................................................................................................................14

4.5.1

Response Time ...................................................................................................................................14

4.5.2

Idle Time .............................................................................................................................................14

4.5.3

Reconfiguration Time ..........................................................................................................................14

4.6

Line Protocol ..............................................................................................................................................15

4.6.1

Invitations To Transmit........................................................................................................................15

4.6.2

Free Buffer Enquiries ..........................................................................................................................15

4.6.3

Data Packets.......................................................................................................................................15

4.6.4

Acknowledgements .............................................................................................................................16

4.6.5

Negative Acknowledgements..............................................................................................................16

Chapter 5

System Description ..............................................................................................................17

5.1

Microcontroller Interface.............................................................................................................................17

5.1.1

Selection of 8/16-Bit Access ...............................................................................................................20

5.1.2

DMA Transfers To And From Internal RAM ........................................................................................20

5.1.3

DMA Operation ...................................................................................................................................21

5.1.4

DMA Data Transfer Sequence (I/O to Memory: Read A Packet) ........................................................25

5.1.5

DMA Data Transfer Sequence (Memory to I/O: Write A Packet).........................................................25

5.1.6

High Speed CPU Bus Timing Support ................................................................................................25

5.2

Transmission Media Interface ....................................................................................................................26

5.2.1

Traditional Hybrid Interface .................................................................................................................27

5.2.2

Backplane Configuration .....................................................................................................................27

5.2.3

Differential Driver Configuration ..........................................................................................................29

5.2.4

Programmable TXEN Polarity .............................................................................................................29

Chapter 6

Functional Description..........................................................................................................31

6.1

Microsequencer..........................................................................................................................................31

6.2

Internal Registers .......................................................................................................................................33

6.2.1

Interrupt Mask Register (IMR) .............................................................................................................33

6.2.2

Data Register ......................................................................................................................................34

6.2.3

Tentative ID Register ..........................................................................................................................34

6.2.4

Node ID Register.................................................................................................................................34

6.2.5

Next ID Register..................................................................................................................................35

6.2.6

Status Register....................................................................................................................................35

6.2.7

Diagnostic Status Register..................................................................................................................35

6.2.8

Command Register .............................................................................................................................35

6.2.9

Address Pointer Registers ..................................................................................................................35

6.2.10

Configuration Register.....................................................................................................................36

6.2.11

Sub-Address Register .....................................................................................................................36

6.2.12

Setup 1 Register..............................................................................................................................36

6.2.13

Setup 2 Register..............................................................................................................................36

6.3

Bus Control Register ..................................................................................................................................37

6.4

DMA Count Register ..................................................................................................................................37

6.5

Internal RAM ..............................................................................................................................................48

6.5.1

Sequential Access Memory.................................................................................................................48

6.5.2

Access Speed .....................................................................................................................................48

6.6

Software Interface ......................................................................................................................................48

6.6.1

Selecting RAM Page Size ...................................................................................................................49

6.6.2

Transmit Sequence .............................................................................................................................50

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