TLV2760, TLV2761, TLV2762, TLV2763, TLV2764, TLV2765

FAMILY OF 1.8 V MICROPOWER RAIL-TO-RAIL INPUT/OUTPUT

OPERATIONAL AMPLIFIERS WITH SHUT DOWN

SLOS326D – JUNE 2000 – REVISED FEBRUARY 2001

18

POST OFFICE BOX 655303

APPLICATION INFORMATION

macromodel information

Macromodel information provided was derived using Microsim Parts

 Release 9.1, the model generation

software used with Microsim PSpice

. The Boyle macromodel (see Note 4) and subcircuit in Figure 36 are

output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):

NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal

of Solid-State Circuits, SC-9, 353 (1974).

*DEVICE=amp_tlv276x_highVdd,OPAMP,NJF,INT

* amp_tlv_276x_highVdd operational amplifier ”macromodel”

* subcircuit updated using Model Editor release 9.1 on 05/15/00

* at 14:40 Model Editor is an OrCAD product.

*

* connections:

non-inverting input

*

| inverting input

*

| | positive power supply

*

| | | negative power supply

*

| | | | output

*

| | | | |

.subckt amp_tlv276x_highVdd

1 2 3 4 5

*

c1

11

12

457.48E–15

c2

6

7

5.0000E–12

css

10

99

1.1431E–12

dc

5

53

dy

de

54

5

dy

dlp

90

91

dx

dln

92

90

dx

dp

4

3

dx

egnd

99

0

poly(2) (3,0) (4,0) 0 .5 .5

fb

7

99

poly(5) vb vc ve vlp vln 0

176.02E6 –1E3 1E3 180E6

–180E6

ga

6

0

11 12 16.272E–6

gcm

0

6

10 99 6.8698E–9

iss

10

4

dc 1.3371E–6

hlim

90

0

vlim 1K

j1

11

2

10 jx1

J2

12

1

10 jx2

r2

6

9

100.00E3

rd1

3

11

61.456E3

rd2

3

12

61.456E3

ro1

8

5

10

ro2

7

99

10

rp

3

4

150.51E3

rss

10

99

149.58E6

vb

9

0

dc 0

vc

3

53

dc .78905

ve

54

4

dc .78905

vlim

7

8

dc 0

vlp

91

0

dc 14.200

vln

0

92

dc 14.200

.model

dx

D(Is=800.00E–18)

.model

dy

D(Is=800.00E–18 Rs=1m Cjo=10p)

.model

jx1

NJF(Is=500.00E–15 Beta=198.03E–6 Vto=–1)

.model

jx2

NJF(Is=500.00E–15 Beta=198.03E–6 Vto=–1)

.ends

IN–

G

D

S

D

S

G

rp

IN+

rd1

rd2

rss

egnd

fb

ro2

ro1

vlim

OUT

ga

ioff

gcm

vb

c1

dc

iss

dp

GND

VDD

css

c2

ve

de

dlp

dln

vln

hlim

vlp

10

4

1

11

12

3

53

54

96

8

5

7

91

90

92

vc

99

+

+

+

+

+

+

+

–

–

–

–

–

–

–

–

+

r2

2

Figure 36. Boyle Macromodel and Subcircuit

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