ST92196A datasheet(171/268 Pages) STMICROELECTRONICS

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- FOUR-CHANNEL I2C BUS INTERFACE (I2C)

I2C BUS INTERFACE (Cont’d)

8.9.2 General Description

In addition to receiving and transmitting data, this

interface convert them from serial to parallel for-

mat and vice versa. The interface is connected,

through a multiplexer, to one I2C bus among 4 by a

data pin, SDAx, and by a clock pin, SCLx, where x

range value is 1 to 4.

It can be connected both with a standard I2C bus

and a Fast I2C bus. This selection is made by soft-

ware.

8.9.2.1 Mode Selection

The interface can operate in the four following

modes:

– Slave transmitter/receiver

– Master transmitter/receiver

By default, it operates in slave mode.

The interface automatically switches from inactive

slave to master after it generates a START condi-

tion and from master to inactive slave in case of ar-

bitration loss or a STOP generation, this allows

Multi-Master capability.

8.9.2.2 Communication Flow

In Master mode, it initiates a data transfer and

generates the clock signal. A serial data transfer

always begins with a start condition and ends with

a stop condition. Start condition is automatically

generated by the interface when the data register

is loaded by the slave address (see register de-

scription for further details). Stop condition is gen-

erated in master mode by writing by software in

the control register.

In Slave mode, the interface is capable of recog-

nising its own address (7-bit), and the General Call

address. The General Call address detection may

be enabled or disabled by software.

Data and addresses are transferred as 8-bit bytes,

MSB first. The first byte following the start condi-

tion is the address byte; it is always transmitted in

Master mode.

A 9th clock pulse follows the 8 clock cycles of a

byte transfer, during which the receiver must send

an acknowledge bit to the transmitter. Refer to Fig-

ure 69.

The acknowledge may be enabled and disabled

by software.

The speed of the I2C interface may be selected

between Standard (15.625 - 100 kHz), Fast I2C

(100- 400 kHz), or Extended I2C (500 - 800 kHz).

Figure 69. I2C bus protocol

SCL

SDA

MSB

ACK

STOP

START

CONDITION

VR02119B

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