ST92196A datasheet(168/268 Pages) STMICROELECTRONICS

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- VIDEO SYNC ERROR DETECTOR (SYNCERR)

8.7 VIDEO SYNC ERROR DETECTOR (SYNCERR)

8.7.1 Functional Description

The Sync Error Detector provides information to

the tuning system whether an IF signal is a picture

carrier or not. The CSYNC source for the detector

is selected using the SYSEL[1:0] bits in the IRSCR

and 2 or directly taken from the SYNDET1 or

SYNDET0 pins.

The number of positive transitions of CSYNC in a

78µsec window is checked. One or two transitions

should occur in every window (horizontal sync

pulses occur at intervals of 63.5µs). An error coun-

ter is incremented at end of a window in case of

one or more of the following situations :

1.No low to high transitions of the signal were de-

tected within the 78µs wide window.

2.More than 2 low-to-high transitions were detect-

ed within the window.

3.More than 2 consecutive samples of CSYNC

taken at 8µs intervals within the window were high.

The errors are accumulated for a period of one

field as defined by two adjacent vertical deflection

pulses. Then the error count for the field is latched

into the SYNCER register and the VALID flag is

set.

The frequency of pulses applied to SYNDET0 or

SYNDET1 input not producing any errors is in the

range of 13KHz to 25Khz. The width of the pulses

applied to these inputs and not producing any er-

rors is less than 16us.

Inevitably, error counts are generated in the verti-

cal sync interval in presence of double frequency

equalization and wide sync pulses. With a stand-

ard video signal the typical error count is 5. The er-

ror count threshold for an acceptable video signal

can be set on basis of experimental results with a

typical value of about 30.

8.7.2 Register Description

SYNC ERROR REGISTER (SYNCER)

R249 - Read only, except bit 7

Reset Value: 0000 0000 (00h)

Bit 7 = VALID:

Data valid bit

This bit is set by hardware on the leading edge of a

vertical deflection pulse. It is cleared by software

Bit 6:0 = SD[6:0]: Sync error count

These bits are updated by hardware on the lead-

ing edge of a vertical deflection pulse.

IR/SYNC CONTROL REGISTER (IRSCR)

R250 - Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = Reserved. Forced by hardware to 0.

Bit 5, 0 = SYSEL[1:0]:

Sync error detector Input

selection

Bit 4:1 = Reserved (used for IR Preprocessor). Re-

fer to the IR Preprocessor chapter.

VALID SD6 SD5 SD4 SD3 SD2 SD1 SD0

SYSEL1

SYSEL0

SYSEL1 SYSEL0

CSYNC signal on SYNDET0

input

CSYNC signal on SYNDET1

input

CSYNC extracted from

CCVIDEO1

CSYNC extracted from

CCVIDEO2

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