TVP7002

SLES206C – MAY 2007 – REVISED APRIL 2013

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VSYNC Width

Subaddress

3Ch

Read only

7

6

5

4

3

2

1

0

Reserved

VSYNC width [4:0]

VSYNC width [4:0]: Number of lines between the leading and trailing edges of the VSYNC input. The VSYNC width along with the HSYNC

and VSYNC polarities can be used to determine whether the input graphics format is using VESA-CVT generated timings.

NOTE: The VSYNC width counter is not dependent on the H-PLL being locked.

Line Length Tolerance

Subaddress

3Dh

Default (03h)

7

6

5

4

3

2

1

0

Reserved

Line length tolerance [6:0]

Line length tolerance [6:0]: Controls sensitivity to HSYNC input stability when using either the internal or external clock reference. Increased

line length tolerance settings may be required for input signals having horizontal instability. This setting may affect the precison of the clock

cycles per line counter (see subaddresses 39h–3Ah)

00h = (minimum) tolerance

03h = (default) tolerance

06h = (recommended) tolerance

7Fh = (maximum) tolerance

Reserved

Subaddress

3Eh

Default (04h)

7

6

5

4

3

2

1

0

Reserved [7:0]

Reserved [7:0]:

04h = Required setting (default)

Video Bandwidth Control

Subaddress

3Fh

Default (00h)

7

6

5

4

3

2

1

0

Reserved

BW select [3:0]

BW select [3:0]: Selectable low-pass filter settings for controlling the analog video bandwidth. This control affects the analog video

bandwidth of all three ADC channels.

0h = Highest video bandwidth (default)

Fh = Lowest video bandwidth (~95 MHz analog video bandwidth )

NOTE: This register can be used to filter high frequency noise but lacks the precision for maximum filtering of various video formats. The

lowest bandwidth setting provides a video bandwidth of at least 50 MHz.

AVID Start Pixel

Subaddress

40h–41h

Default (012Ch)

Subaddress

7

6

5

4

3

2

1

0

40h

AVID start [7:0]

41h

Reserved

AVID active

AVID start [12:8]

AVID active

0 = AVID out active during VBLK (default)

1 = AVID out inactive during VBLK

AVID start [12:0]: AVID start pixel number, this is an absolute pixel location from the leading edge of HSYNC (start pixel 0). The TVP7002

updates the AVID start only when the AVID start MSB byte is written to.

AVID start pixel register also controls the position of SAV code. The TVP7002 inserts the SAV code four pixels before the pixel number

specified in the AVID start pixel register.

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