TVP7002IPZP datasheet(31/58 Pages) TI1

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TVP7002

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SLES206C – MAY 2007 – REVISED APRIL 2013

H-PLL and Clamp Control

Subaddress

0Fh

Default (2Eh)

Coast Sel

CPO

CPC

SMO

FCPD

ADC Test

CF: Clamp Function. Clamp pulse select. This control bit determines whether the timing for both the fine clamp and the ALC circuit are

generated internally or externally.

0 = Internal fine clamp and ALC timing (default)

1 = External fine clamp and ALC timing (pin 76)

CP: Clamp Polarity. External clamp polarity select

0 = Active-high clamp pulse (default)

1 = Active-low clamp pulse

CS: Coast Select. Coast signal select. This control bit determines whether the timing for H-PLL coast signal is generated internally or

externally.

0 = External H-PLL coast timing (pin 77)

1 = Internal H-PLL coast timing (default)

CPO: Coast Polarity Override

0 = Polarity determined by chip (default)

1 = Polarity set be Bit 3 in register 0Fh

CPC: Coast Polarity Change. External coast polarity select

0 = Active-low coast signal

1 = Active-high coast signal (default)

SMO: Seek Mode Override. Places the TVP7002 in a low power mode whenever no activity is detected on the selected sync inputs.

0 = Enable automatic power management mode

1 = Disable automatic power management mode (default)

NOTE: Digital outputs are not high impedance and may be in a random state during low power mode. Outputs can be put

in high impedance state by I2C register 17h.

FCPD: Full Chip Power Down. Active-low power down. FCPD powers down all blocks except I2C. The I2C register values are retained.

0 = Power-down mode

1 = Normal operation (default)

NOTE: Digital outputs are not high impedance and may be in random state during FCPD. Outputs can be put in high

impedance state by I2C register 17h.

ADC Test: Active-high ADC test mode select. When placed in the ADC test mode, the TVP7002 disables the fine clamp, enables the

coarse clamp, and selects the external clock input (pin 80) for each ADC channel.

0 = ADC test mode disabled (default)

1 = ADC test mode enabled

NOTE: Also see the Horizontal PLL Control register at subaddress 03h.

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