TUSB7320 datasheet(6/117 Pages) TI1

6 / 117 page

TUSB7320, TUSB7340

SLLSE76M – MARCH 2011 – REVISED JULY 2015

www.ti.com

Clock and Reset Signals (continued)

I/O

DESCRIPTION

TUSB7320

TUSB7340

NAME

NO.

USB SuperSpeed receiver differential pair (negative).

USB_SSRXN_DN2

A10

Note: When routing, it is permissible to swap the positive and negative signals in Port 2 SSRX

differential pair.

USB_DP_DN2

B12

I/O

USB High-speed differential transceiver (positive).

USB_DM_DN2

A13

I/O

USB High-speed differential transceiver (negative).

USB DS Port 2 Power On Control for Downstream Power. The terminal is used for control of the

PWRON2#

B34

downstream power switch. If the PWRON_POLARITY bit is set to 1, this pin is active high and the

internal pulldown is disabled. This pin may be at low impedance when power rails are removed.

USB DS Port 2 Overcurrent Detection.

OVERCUR2#

A37

0: overcurrent detected;

1: overcurrent not detected

USB SuperSpeed transmitter differential pair (positive).

USB_SSTXP_DN3

—

B28

Note: When routing, it is permissible to swap the positive and negative signals in Port 3 SSTX

differential pair.

USB SuperSpeed transmitter differential pair (negative).

USB_SSTXN_DN3

—

A30

Note: When routing, it is permissible to swap the positive and negative signals in Port 3 SSTX

differential pair.

USB SuperSpeed receiver differential pair (positive).

USB_SSRXP_DN3

—

B27

Note: When routing, it is permissible to swap the positive and negative signals in Port 3 SSRX

differential pair.

USB SuperSpeed receiver differential pair (negative).

USB_SSRXN_DN3

—

A29

Note: When routing, it is permissible to swap the positive and negative signals in Port 3 SSRX

differential pair.

USB_DP_DN3

—

B25

I/O

USB High-speed differential transceiver (positive).

USB_DM_DN3

—

A27

I/O

USB High-speed differential transceiver (negative).

USB DS Port 3 Power On Control for Downstream Power. The terminal is used for control of the

PWRON3#

—

A46

downstream power switch. If the PWRON_POLARITY bit is set to 1, this pin is active high and the

internal pulldown is disabled. This pin may be at low impedance when power rails are removed.

USB DS Port 3 Overcurrent Detection.

OVERCUR3#

—

B43

0: overcurrent detected;

1: overcurrent not detected

USB SuperSpeed transmitter differential pair (positive).

USB_SSTXP_DN4

—

Note: When routing, it is permissible to swap the positive and negative signals in Port 4 SSTX

differential pair.

USB SuperSpeed transmitter differential pair (negative).

USB_SSTXN_DN4

—

Note: When routing, it is permissible to swap the positive and negative signals in Port 4 SSTX

differential pair.

USB SuperSpeed receiver differential pair (positive).

USB_SSRXP_DN4

—

Note: When routing, it is permissible to swap the positive and negative signals in Port 4 SSRX

differential pair.

USB SuperSpeed receiver differential pair (negative).

USB_SSRXN_DN4

—

Note: When routing, it is permissible to swap the positive and negative signals in Port 4 SSRX

differential pair.

USB_DP_DN4

—

I/O

USB High-speed differential transceiver (positive).

USB_DM_DN4

—

I/O

USB High-speed differential transceiver (negative).

USB DS Port 4 Power On Control for Downstream Power. The terminal is used for control of the

PWRON4#

—

A48

downstream power switch. If the PWRON_POLARITY bit is set to 1, this pin is active high and the

internal pulldown is disabled. This pin may be at low impedance when power rails are removed.

USB DS Port 4 Overcurrent Detection.

OVERCUR4#

—

B45

0: overcurrent detected;

1: overcurrent not detected

I2C SIGNALS

SCL

I/O

I2C Clock - If no I2C device is present, pull this line down to disable.

SDA

I/O

I2C Data - If no I2C device is present, pull this line down to disable.

TEST AND MISCELLANEOUS SIGNALS

JTAG_TCK

A32

JTAG test clock

JTAG_TDI

A35

JTAG test data in

JTAG_TDO

B31

JTAG test data out

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