TUSB7320 datasheet(49/117 Pages) TI1

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TUSB7320, TUSB7340

www.ti.com

SLLSE76M – MARCH 2011 – REVISED JULY 2015

7.5.1.54 GPIO Data Register

This register is used to read the state of the GPIO pins and to change the state of GPIO pins that are in output

mode. Writing to a bit that is in input mode will be ignored. The default value at power up depends on the state of

the GPIO terminals as they default to general purpose inputs. This register is reset by a PCI Express reset

(PERST#), a GRST#, or the internally-generated power-on reset.

PCI register offset: B6h

Default value: 0000h

Table 85. PCI Register B6h

Bit

No.

Reset

State

Table 86. GPIO Data Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:4

RSVD

Reserved. Returns zero when read.

GPIO 3 Data. This bit is used to read the state of GPIO3 or change the

GPIO3_DATA(1)

state of GPIO3 in output mode.

GPIO 2 Data. This bit is used to read the state of GPIO2 or change the

GPIO2_DATA(1)

state of GPIO2 in output mode.

GPIO 1 Data. This bit is used to read the state of GPIO1 or change the

GPIO1_DATA(1)

state of GPIO1 in output mode.

GPIO 0 Data. This bit is used to read the state of GPIO0 or change the

GPIO0_DATA(1)

state of GPIO0 in output mode.

(1)

This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on reset.

7.5.1.55 MSI-X Capability ID Register

This read-only register identifies the linked list item as the register for MSI-X Capabilities. The register returns

11h when read.

PCI register offset: C0h

Default value: 11h

Table 87. PCI Register C0h

Bit No.

Reset State

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