TUSB7320 datasheet(39/117 Pages) TI1

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TUSB7320, TUSB7340

www.ti.com

SLLSE76M – MARCH 2011 – REVISED JULY 2015

7.5.1.39 Device Capabilities Register

The Device Capabilities Register indicates the device specific capabilities of the TUSB73X0.

PCI register offset: 74h

Default value: 0000 8FC3h

Table 57. PCI Register 74h

Bit

No.

Reset

State

Bit

No.

Reset

State

Table 58. Device Capabilities Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:29

RSVD

Reserved. Return zeros when read.

Function Level Reset. This bit is set to 0 because the TUSB73X0 has

FLR

only one function.

Captured Slot Power Limit Scale. The value in this register is

programmed by the host by issuing a Set_Slot_Power_Limit Message.

When a Set_Slot_Power_Limit Message is received bits 9:8 are written

to this field. The value in this register specifies the scale used for the Slot

27:26

CSPLS

Power Limit.

00 – 1.0x

01 – 0.1x

10 – 0.01x

11 – 0.001x

Captured Slot power Limit Value. The value in this register is

programmed by the host by issuing a Set_Slot_Power_Limit Message.

When a Set_Slot_Power_Limit Message is received bits 7:0 are written

25:18

CSPLV

to this field. The value in this register in combination with the Slot power

Limit Scale value, specifies the upper limit of power supplied to the slot.

The power limit is calculated by multiplying the value in this field by the

value in the Slot Power Limit Scale field.

17:16

RSVD

Reserved. Return zeros when read.

Role Based Error Reporting. This bit is hardwired to 1 indicating that the

RBER

TUSB73X0 supports Role Based Error Reporting

14:12

RSVD

Reserved. Return zeros when read.

Endpoint L1 Acceptable Latency. This field indicates the acceptable

latency for a transition from L1 to L0 State. This field can be programmed

by writing to the L1_LATENCY field in the General Control Register 2.

11:9

EP_L1_LAT

The default value for this register is the latency for the PHY to exit the L1

state. This field cannot be programmed to be less than the latency for the

PHY to exit the L1 state.

Endpoint L0s Acceptable Latency. This field indicates the acceptable

latency for a transition from L0s to L0 State. This field can be

programmed by writing to the L0s_LATENCY field in the General Control

8:6

EP_L0S_LAT

to exit the L0s state. This field cannot be programmed to be less than the

latency for the PHY to exit the L0s state.

Extended Tag Field Supported. This field indicates the size of the tag

ETFS

field and is encoded as 0.

Phantom Functions Supported. This field is read only 00b indicating that

4:3

PFS

function numbers are not used for phantom functions.

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