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ASX340CS датащи(PDF) 57 Page - ON Semiconductor

номер детали ASX340CS
подробное описание детали  1/4-Inch Color CMOS NTSC/PAL Digital Image SOc
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ASX340CS датащи(HTML) 57 Page - ON Semiconductor

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ASX340CS_DS Rev. F Pub. 6/15 EN
57
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 39:
Power Up Sequence
Notes:
1. RESET_BAR may not exceed VDD_IO + 0.3V.
2. The 2.8V plane (VAA, VAA_PIX, VDD_PLL, VDD_DAC, VDD_IO) must remain at a higher voltage than
the 1.8V core voltage at all times.
Notes:
1. Xtal settling time is component-dependent (Xtal, Oscillator, and so on) and usually takes about
10ms ~100ms.
2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are
required for the sensor itself, assuming all power rails are settled. In a circuit where Hard reset is
performed by the RC circuit, then the RC time must include the all power rail settle time and Xtal.
Table 29:
Power Up Sequence
Definition
Symbol
Minimum
Typical
Maximum
Unit
VDD_PLL to VAA/VAA_PIX
t0
0
–
–
s
VAA/VAA_PIX to VDD_IO
t1
0
–
–
s
VDD_IO to VDD
t2
0
–
–
s
Xtal settle time
tx
–
301
–ms
Hard Reset
t3
102
––
Clock cycle
Internal Initialization
t4
50
–
–
ms
VDD (1.8)
VAA_PIX
VAA (2.8)
VDD_PLL
VDD_DAC (2.8)
EXTCLK
RESET_BAR
VDD_IO (2.8)
t3
t4
t5
t0
t1
Hard Reset
Internal
(NTSC/PAL)
Initialization
Patch Config
SPI or Host
Streaming
t2
tx



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