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ASX340CS датащи(PDF) 54 Page - ON Semiconductor

номер детали ASX340CS
подробное описание детали  1/4-Inch Color CMOS NTSC/PAL Digital Image SOc
PDF  74 Pages
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ASX340CS датащи(HTML) 54 Page - ON Semiconductor

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ASX340CS_DS Rev. F Pub. 6/15 EN
54
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
I/O Timing
Digital Output
By default, the ASX340CS launches pixel data, FV, and LV synchronously with the falling
edge of PIXCLK. The expectation is that the user captures data, FV, and LV using the
rising edge of PIXCLK. The timing diagram is shown in Figure 36.
As an option, the polarity of the PIXCLK can be inverted from the default by program-
ming R0x0016[14].
Figure 36:
Digital Output I/O Timing
Note:
PIXCLK can be inverted from the default by programming R0x0016[14].
Table 26:
Parallel Digital Output I/O Timing
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; Default slew rate
Signal
Parameter
Conditions
Min
Typ
Max
Unit
EXTCLK
fextclk
max ±100 ppm
6
27
54
MHz
textclk_period
18.52
37
166.67
ns
Duty cycle
45
50
55
%
PIXCLK1
fpixclk
6
27
54
MHz
tpixclk_period
18.52
37.04
166.67
ns
Duty cycle
45
50
55
%
DATA[7:0]
tpixclkf_dout
1.55
–
1.9
ns
tdout_su
18
–
20
ns
tdout_ho
18
–
20
ns
FV/LV
tpixclkf_fvlv
1.6
–
3.05
ns
tfvlv_su
15
–
16
ns
tfvlv_ho
20
–
21
ns
EXT CLK
PIXC LK
D OUT [7:0]
F R AM E_VALID
LIN E _VALID
t
pixclkf_dout
t
pixclkf_fvlv
Input
O utput
O utput
O utput
t
fvlv_su
t
fvlv_ho
t
dout_ho
t
dout_su
t
extclk_period



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