AP0101CS datasheet(30/42 Pages) ONSEMI

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AP0101CS/D Rev. 7, 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0101CS HDR: Image Signal Processor (ISP)

Protocol

Stop Condition

A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.

Typical Operation

A typical READ or WRITE sequence begins by the master generating a start condition on

the bus. After the start condition, the master sends the 8-bit slave address/data direction

byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0”

indicates a WRITE and a “1” indicates a READ. If the address matches the address of the

slave device, the slave device acknowledges receipt of the address by generating an

acknowledge bit on the bus.

If the request was a WRITE, the master then transfers the 16-bit register address to which

a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave

sends an acknowledge bit after each sequence to indicate that the byte has been

received. The master will then transfer the 8-bit or 16-bit data, as one or two 8-bit

sequences and the slave sends an acknowledge bit after each sequence to indicate that

the byte has been received. The master stops writing by generating a (re)start or stop

condition. If the request was a READ, the master sends the 8-bit write slave address/data

direction byte and 16-bit register address, just as in the write request. The master then

generates a (re)start condition and the 8-bit read slave address/data direction byte, and

clocks out the register data, 8 bits at a time. The master generates an acknowledge bit

after each 8-bit transfer. The data transfer is stopped when the master sends a no-

acknowledge bit.

Single READ from Random Location

Figure 16 shows the typical READ cycle of the host to the AP0101CS. The first two bytes

sent by the host are an internal 16-bit register address. The following 2-byte READ cycle

sends the contents of the registers to host.

Figure 16:

Single READ from Random Location

S = start condition

P = stop condition

Sr = restart condition

A = acknowledge

A = no-acknowledge

slave to master

master to slave

Slave Address

A Reg Address[15:8]

Reg Address[7:0]

Slave Address

Read Data

[15:8]

Previous Reg Address, N

Reg Address, M

M+1

Read Data

[7:0]

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