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AP0101CS датащи(PDF) 28 Page - ON Semiconductor |
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AP0101CS датащи(HTML) 28 Page - ON Semiconductor |
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28 / 42 page ![]() AP0101CS/D Rev. 7, 1/16 EN 28 ©Semiconductor Components Industries, LLC,2016. AP0101CS HDR: Image Signal Processor (ISP) Sensor Embedded Data ALTM Bayer Output The data ordering for the ALTM Bayer output modes for AP0101CS are shown in Table 15. ALTM Bayer modes are selected by setting cam_mode_select = 7 (ALTM Bayer 12) or 8 (ALTM Bayer 10). Table 15 and Table 16 show LSB aligned data; it is possible by using a register setting to obtain MSB aligned data. The data ordering for the Bayer output modes for AP0101CS are shown in Table 16. Note: Raw Bayer mode can be selected by setting cam_mode_select = 0x4. Sensor Embedded Data The AP0101CS is capable of passing sensor embedded data in Bayer output mode only. The AP0101CS Statistics are available through the serial interface. Refer to the Developer Guide for details. Slave Two-Wire Serial Interface The two-wire slave serial interface bus enables read/write access to control and status registers within the AP0101CS. The interface protocol uses a master/slave model in which a master controls one or more slave devices. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements, as follows: • a start or restart condition • a slave address/data direction byte • a 16-bit register address • an acknowledge or a no-acknowledge bit •data bytes • a stop condition The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Table 15: ALTM Bayer Output Modes Mode Byte D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ALTM_Bayer_10 Single 0 0 0 0 0 0 D9D8D7D6D5D4D3D2D1D0 ALTM_Bayer_12 Single 0 0 0 0 D11 D10 D9D8D7D6D5D4D3D2D1D0 Table 16: Bayer Output Modes Mode Byte D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Raw_Bayer_1 2 Single 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 |
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