CS5376A datasheet(34/107 Pages) CIRRUS

34 / 107 page

CS5376A

9.3.2

SPI 1 registers

The SPI 1 registers are shown in Figure 19 and are

24-bit registers mapped into an 8-bit register space

as high, mid, and low bytes. See “SPI 1 Registers”

on page 82 for the bit definitions of the SPI 1 reg-

isters.

9.3.3

SPI 1 transactions

A serial transaction to the SPI 1 registers starts with

an SPI opcode, followed by an address, and then

some number of data bytes written or read starting

at that address.

Typical serial write transactions require sending

groups of 5, 8, or 11 total bytes to the SPI1CMD or

SPI1DAT1 registers.

Example 5-byte write transaction to SPI1CMD

02 03 12 34 56

Example 5-byte write transaction to SPI1DAT1

02 06 12 34 56

Example 8-byte write transaction to SPI1CMD

02 03 12 34 56 AB CD EF

Example 8-byte write transaction to SPI1DAT1

02 06 12 34 56 AB CD EF

Example 11-byte write transaction to SPI1CMD

02 03 12 34 56 AB CD EF 65 43 21

Typical serial read transactions require groups of 3

or 5 bytes, split between writing into MOSI and

reading from MISO.

3-byte read transaction of mid-byte of SPI1CTRL

MOSI: 03 01 00

MISO: xx xx 12

5-byte read transaction of SPI1DAT1

MOSI: 03 06 00 00 00

MISO: xx xx 12 34 56

9.3.4

Multiple serial transactions

Some configuration commands require multiple se-

rial transactions to complete. There must be a small

delay between transactions for the CS5376A to

process the incoming data. Three methods can be

used to ensure the CS5376A is ready to receive the

next configuration command.

1) Delay a fixed 1 ms period to guarantee enough

time for the command to be completed.

2) Monitor the SINT pin for a 1 us active low pulse.

This pulse output occurs once the CS5376A com-

pletes processing the current command.

3) Verify the status of the E2DREQ bit by reading

the SPI1CTRL register. When low, the CS5376A is

ready for the next command.

9.3.5

Polling E2DREQ

One transaction type that can always be performed

no matter the delay from the previous configuration

command is reading E2DREQ in the mid-byte of

the SPI1CTRL register. A 3-byte read transaction.

MOSI: 03 01 00

MISO: xx xx 01

<- E2DREQ bit high

MISO: xx xx 00

<- E2DREQ bit low

Name

Addr.

Type

# Bits

Description

SPI1CTRL

00 - 02

R/W

8, 8, 8

SPI 1 Control

SPI1CMD

03 - 05

R/W

8, 8, 8

SPI 1 Command

SPI1DAT1

06 - 08

R/W

8, 8, 8

SPI 1 Data 1

SPI1DAT2

09 - 0B

R/W

8, 8, 8

SPI 1 Data 2

Figure 19. SPI 1 Registers

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