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CS5376A датащи(PDF) 68 Page - Cirrus Logic |
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CS5376A датащи(HTML) 68 Page - Cirrus Logic |
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68 / 107 page ![]() CS5376A 68 18. TIME BREAK CONTROLLER A time break signal is used to mark timing events that occur during measurement. An external signal sets a flag in the status byte of an output sample to mark when the external event occurred. A rising edge input to the TIMEB pin causes the TB timing reference flag to be set in the SD port status byte. When set, the TB flag appears for only one output sample in the status byte of all enabled channels. The TB flag output can be delayed by programming a sample delay value into the TIME- BRK digital filter register. 18.1 Pin Description TIMEB - Pin 57 Time break input pin, rising edge triggered. 18.2 Time Break Operation An externally generated timing reference signal ap- plied to the TIMEB pin initiates an internal sample counter. After a number of output samples have passed, programmed in the TIMEBRK digital filter register (0x29), the TB flag is set in the status byte of the SD port output word for all enabled channels. The TB flag is automatically cleared for subse- quent data words, and appears for only one output sample in each channel. 18.3 Time Break Delay The TIMEBRK register (0x29) sets a sample delay between a received rising edge on the TIMEB pin and writing the TB flag into the SD port status byte. The programmable sample counter can compensate for group delay through the digital filters. When the proper group delay value is programmed into the TIMEBRK register, the TB flag will be set in the status byte of the measurement sample taken when the timing reference signal was received. 18.3.1 Step Input and Group Delay A simple method to empirically measure the step response and group delay of a CS5376A measure- ment channel is to use the time break signal as both a timing reference input and an analog step input. When a rising edge is received on the TIMEB pin with no delay programmed into the TIMEBRK reg- ister, the TB flag is set in the next SD port status byte. The same rising edge can act as a step input to the analog channel, propagating through the digital filter to appear as a rising edge in the measurement data. By comparing the timing of the TB status flag output and the rising edge in the measurement data, the measurement channel group delay can be deter- mined. TIMEB in SD Port Status Byte Delay Counter TIMEBRK TB Flag Figure 37. Time Break Block Diagram |
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