CS5376A datasheet(71/107 Pages) CIRRUS

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CS5376A

20. SERIAL PERIPHERAL INTERFACE 2

The Serial Peripheral Interface 2 (SPI 2) port is a

master mode SPI port designed to interface with se-

rial peripherals. By writing the SPI2 digital filter

registers, multiple serial slave devices can be con-

trolled through the CS5376A.

20.1 Pin Descriptions

CS[4:0] - Pins 32 - 36

Serial chip selects. Multiplexed with GPIO pins.

SCK2 - Pin 31

Serial clock output, common to all channels.

SO - Pin 30

Serial data output, common to all channels.

SI[4:1] - Pins 26 - 29

Serial data inputs.

20.2 SPI 2 Architecture

The SPI 2 pin interface has multiple chip selects

and serial data inputs, but a common serial clock

and serial data output. Which chip select and serial

input to use for a particular slave serial transaction

is selected by bits in the SPI2CTRL digital filter

SPI 2 chip select outputs are multiplexed with

GPIO pins, which cannot perform both functions

simultaneously. When used as a chip select, the

GPIO output must be programmed high to permit

the chip select to operate as an active low signal.

See “General Purpose I/O” on page 69 for informa-

tion about programming the GPIO pins.

The SPI 2 interface transfers data from the SPI 2

registers to a slave serial device and back through a

bi-directional 8-bit shift register. Serial transac-

tions are automatic once control, command, and

data values are written into the SPI 2 digital filter

registers.

20.3 SPI 2 Registers

SPI 2 transactions are initiated by first writing

command, address, and data values to the

SPI2CMD and SPI2DAT digital filter registers,

and then writing the SPI2CTRL register to set the

D2SREQ bit. The D2SREQ bit initiates a serial

Figure 39. Serial Peripheral Interface 2 (SPI 2) Block Diagram

SCK2

SI4

CS1

CS2

CS3

CS4

Pin logic

Select

SI2

SI1

SI3

logic

SPI2EN[4:1] / RCH[1:0]

4:1

CS0

Digital

Filter

CS[4:0]

SCKFS[2:0] / SCKPO / SCKPH

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