ST16C580CP40 datasheet(20/41 Pages) EXAR

20 / 41 page

ST16C580

Rev. 1.20

(FIFO’s enabled, FCR bit-0 = logic 1, FCR bit-3 = logic

0) and when there are no characters in the transmit

FIFO or transmit holding register, the -TXRDY pin will

be a logic 0. Once active the -TXRDY pin will go to a

logic 1 after the first character is loaded into the

transmit holding register.

Receive operation in mode “0”:

When the 580 is in mode “0” (FCR bit-0 = logic 0) or

in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 =

logic 0) and there is at least one character in the

receive FIFO, the -RXRDY pin will be a logic 0. Once

active the -RXRDY pin will go to a logic 1 when there

are no more characters in the receiver.

Transmit operation in mode “1”:

When the 580 is in FIFO mode ( FCR bit-0 = logic 1,

FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1

when the transmit FIFO is completely full. It will be a

logic 0 if one or more FIFO locations are empty.

Receive operation in mode “1”:

When the 580 is in FIFO mode (FCR bit-0 = logic 1,

FCR bit-3 = logic 1) and the trigger level has been

reached, or a Receive Time Out has occurred, the -

RXRDY pin will go to a logic 0. Once activated, it will

go to a logic 1 after there are no more characters in the

FIFO.

FCR BIT 4-5: (logic 0 or cleared is the default condi-

tion, TX trigger level = 1)

These bits are used to set the trigger level for the

transmit FIFO interrupt. The ST16C580 will issue a

transmit empty interrupt when the number of charac-

ters in FIFO drops below the selected trigger level.

BIT-5

BIT-4

TX FIFO trigger level

FCR BIT 6-7: (logic 0 or cleared is the default condi-

tion, RX trigger level =8)

These bits are used to set the trigger level for the receive

FIFO interrupt.

An interrupt is generated when the number of charac-

ters in the FIFO equals the programmed trigger level.

However the FIFO will continue to be loaded until it is

full.

BIT-7

BIT-6

RX FIFO trigger level

Interrupt Status Register (ISR)

The 580 provides six levels of prioritized interrupts to

minimize external software interaction. The Interrupt

Status Register (ISR) provides the user with six inter-

rupt status bits. Performing a read cycle on the ISR will

provide the user with the highest pending interrupt

level to be serviced. No other interrupts are acknowl-

edged until the pending interrupt is serviced. When-

ever the interrupt status register is read, the interrupt

status is cleared. However it should be noted that only

the current pending interrupt is cleared by the read. A

lower level interrupt may be seen after rereading the

interrupt status bits. The Interrupt Source Table 6

(below) shows the data values (bit 0-5) for the six

prioritized interrupt levels and the interrupt sources

associated with each of these interrupt levels:

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