ST16C580CP40 datasheet(19/41 Pages) EXAR

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ST16C580

Rev. 1.20

(normal default condition)

Logic 1 = Enable the receiver line status interrupt.

IER BIT-3:

Logic 0 = Disable the modem status register interrupt.

(normal default condition)

Logic 1 = Enable the modem status register interrupt.

IER BIT -4:

Logic 0 = Disable sleep mode. (normal default condi-

tion)

Logic 1 = Enable sleep mode. See Sleep Mode section

for details

IER BIT-5:

Logic 0 = Disable the software flow control, receive

Xoff interrupt. (normal default condition)

Logic 1 = Enable the software flow control, receive

Xoff interrupt. See Software Flow Control section for

details.

IER BIT-6:

Logic 0 = Disable the RTS interrupt. (normal default

condition)

Logic 1 = Enable the RTS interrupt. The 580 issues an

interrupt when the RTS pin transitions from a logic 0

to a logic 1.

IER BIT-7:

Logic 0 = Disable the CTS interrupt. (normal default

condition)

Logic 1 = Enable the CTS interrupt. The 580 issues an

interrupt when CTS pin transitions from a logic 0 to a

logic 1.

FIFO Control Register (FCR)

This register is used to enable the FIFO’s, clear the

FIFO’s, set the transmit/receive FIFO trigger levels,

and select the DMA mode. The DMA, and FIFO

modes are defined as follows:

DMA MODE

Mode 0

Set and enable the interrupt for each

single transmit or receive operation, and is similar to

the ST16C450 mode. Transmit Ready (-TXRDY) will

go to a logic 0 when ever an empty transmit space is

available in the Transmit Holding Register (THR).

Receive Ready (-RXRDY) will go to a logic 0 when-

ever the Receive Holding Register (RHR) is loaded

with a character.

Mode 1

Set and enable the interrupt in a block

mode operation. The transmit interrupt is set when the

transmit FIFO is below the programmed trigger level.

-TXRDY remains a logic 0 as long as one empty FIFO

location is available. The receive interrupt is set when

the receive FIFO fills to the programmed trigger level.

However the FIFO continues to fill regardless of the

programmed level until the FIFO is full. -RXRDY

remains a logic 0 as long as the FIFO fill level is above

the programmed trigger level.

FCR BIT-0:

Logic 0 = Disable the transmit and receive FIFO.

(normal default condition)

Logic 1 = Enable the transmit and receive FIFO. This

bit must be a “1” when other FCR bits are written to or

they will not be programmed.

FCR BIT-1:

Logic 0 = No FIFO receive reset. (normal default

condition)

Logic 1 = Clears the contents of the receive FIFO and

resets the FIFO counter logic (the receive shift regis-

ter is not cleared or altered). This bit will return to a

logic 0 after clearing the FIFO.

FCR BIT-2:

Logic 0 = No FIFO transmit reset. (normal default

condition)

Logic 1 = Clears the contents of the transmit FIFO and

resets the FIFO counter logic (the transmit shift regis-

ter is not cleared or altered). This bit will return to a

logic 0 after clearing the FIFO.

FCR BIT-3:

Logic 0 = Set DMA mode “0”. (normal default condi-

tion)

Logic 1 = Set DMA mode “1.”

Transmit operation in mode “0”:

When the 580 is in the ST16C450 mode (FIFO’s

disabled, FCR bit-0 = logic 0) or in the FIFO mode

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