PCM1602 datasheet(27/29 Pages) TI

27 / 29 page

PCM1602

SBAS163

THEORY OF OPERATION

The DAC section of the PCM1602 is based on a multi-bit

delta-sigma architecture. This architecture utilizes a fourth-

order noise shaper and an 8-level amplitude quantizer, fol-

lowed by an analog low-pass filter. A block diagram of the

delta-sigma modulator is shown in Figure 19. This architec-

ture has the advantage of stability and improved jitter toler-

ance, when compared to traditional 1-bit (2-level) delta-

sigma designs.

The combined oversampling rate of the digital interpolation

filter and the delta-sigma modulator is 32, 64, or 128fS. The

total oversampling rate is determined by the desired sam-

pling frequency. If fS ≤ 96kHz, then the OVER bit in

128fS. If fS > 96kHz, then the OVER bit may be used to set

the oversampling rate to 32 or 64fS. Figure 20 shows the

out-of-band quantization noise plots for both the 64x and

128x oversampling scenarios. Notice that the 128x

oversampling plot shows significantly improved out-of-band

noise performance, allowing for a simplified low-pass filter

to be used at the output of the DAC.

Figure 18 illustrates the simulated jitter sensitivity of the

PCM1602. To achieve best performance, the system clock

jitter should be less than 300 picoseconds. This is easily

achieved using a quality clock generation IC, like the PLL1700

from Texas Instruments.

FIGURE 18. Jitter Sensitivity.

FIGURE 19. Eight-Level Delta-Sigma Modulator.

100

200

300

400

500

600

125

120

115

110

105

100

Jitter (ps)

JITTER DEPENDENCE (x 64 Over Sampling)

Z–1

8-Level Quantizer

Z–1

–

Z–1

64f

FIGURE 20. Quantization Noise Spectrum.

–20

–40

–60

–80

–100

–120

–140

–160

–180

Frequency (f

QUANTIZATION NOISE SPECTRUM

(64x Oversampling)

QUANTIZATION NOISE SPECTRUM

(128x Oversampling)

–20

–40

–60

–80

–100

–120

–140

–160

–180

Frequency (f

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