PCM1602 datasheet(11/29 Pages) TI

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PCM1602

SBAS163

The PCM1602 also includes an external reset capability

using the RST input (pin 37). This allows an external

controller or master reset circuit to force the PCM1602 to

initialize to its reset default state. For normal operation,

RST should be set to a logic “1”.

The external reset operation and timing is shown in Figure 3.

The RST pin is set to logic “0” for a minimum of 20ns.

After the initialization sequence is completed, the PCM1602

will be set to its reset default state, as described in the

Mode Control Registers section of this data sheet.

During the reset period (1024 system clocks), the analog

outputs are forced to the bipolar zero level (or VCC/2).

After the reset period, the internal registers are initialized

in the next 1/fS period and, if SCKI, BCK, and LRCK are

provided continuously, the PCM1602 provides proper ana-

log output with unit-group delay, as specified in this data

sheet.

The external reset is especially useful in applications

where there is a delay between PCM1602 power-up and

system clock activation. In this case, the RST pin should

be held at a logic “0” level until the system clock has been

activated.

AUDIO SERIAL INTERFACE

The audio serial interface for the PCM1602 is comprised of

a 5-wire synchronous serial port. It includes LRCK (pin 41),

BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46), and

DATA3 (pin 47). BCK is the serial audio bit clock, and is

used to clock the serial data present on DATA1, DATA2,

and DATA3 into the audio interface’s serial shift register.

Serial data is clocked into the PCM1602 on the rising edge

of BCK. LRCK is the serial audio left/right clock. It is used

to latch serial data into the serial audio interface’s internal

registers.

Both LRCK and BCK must be synchronous to the system

clock. Ideally, it is recommended that LRCK and BCK be

derived from the system clock input, SCKI. LRCK is

operated at the sampling frequency (fS). BCK may be oper-

ated at 32, 48, or 64 times the sampling frequency (I2S format

does not support BCK = 32fS).

Internal operation of the PCM1602 is synchronized with

LRCK. Accordingly, it is held when the sampling rate clock

of LRCK is changed, or SCKI and/or BCK is broken at least

for one clock cycle. If SCKI, BCK, and LRCK are provided

continuously after this hold condition, the internal operation

will be resynchronized automatically, less than 3/fS period. In

this resynchronize period, and following 3/fS, the analog

outputs are forced to the bipolar zone level (or VCC/2).

External resettling is not required.

AUDIO DATA FORMATS AND TIMING

The PCM1602 supports industry-standard audio data formats,

including Standard, I2S, and Left-Justified (see Figure 4).

Data formats are selected using the format bits, FMT[2:0], in

formats require Binary Two’s Complement, MSB-first audio

data. See Figure 5 for a detailed timing diagram of the serial

audio interface.

DATA1, DATA2, and DATA3 each carry two audio chan-

nels, designated as the Left and Right channels. The Left

channel data always precedes the Right channel data in the

serial data stream for all data formats. Table II shows the

mapping of the digital input data to the analog output pins.

DATA INPUT

CHANNEL

ANALOG OUTPUT

DATA1

Left

VOUT1(1)

DATA1

Right

VOUT2(1)

DATA2

Left

VOUT3(2)

DATA2

Right

VOUT4(2)

DATA3

Left

VOUT5(2)

DATA3

Right

VOUT6(2)

NOTES: (1) Up to 192kHz. (2) Up to 96kHz.

TABLE II. Audio Input Data to Analog Output Mapping.

FIGURE 3. External Reset Timing.

1024 System Clocks

Reset

Reset Removal

System Clock

Internal Reset

RST

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