TMS320VC5510 datasheet(28/86 Pages) TI

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Functional Overview

June 2000 − Revised July 2004

SPRS076J

3.2.2 Direct Memory Access (DMA)

The 5510 DMA provides the following features:

•

Four standard ports, one for each of the following data resources: DARAM, SARAM, Peripherals, and

External Memory

•

Six channels, which allow the DMA controller to track the context of six independent DMA channels

•

Programmable low/high priority for each DMA channel

•

One interrupt for each DMA channel

•

Event synchronization. DMA transfers in each channel can be dependent on the occurrence of selected

events.

•

Programmable address modification for source and destination addresses

•

Dedicated Idle Domain allows the DMA controller to be placed in a low-power (idle) state under software

control.

•

DMA controller supports EHPI accesses to internal/external memory

The 5510 DMA controller allows transfers to be synchronized to selected events. The 5510 supports

14 separate sync events and each channel can be tied to separate sync events independent of the other

channels. Sync events are selected by programming the SYNC field in the channel-specific DMA Channel

Control Register (DMA_CCR). The sync events available on the 5510 are shown in Table 3−6.

For more information on the 5510 DMA, see the TMS320VC5503/5507/5509/5510 DSP Direct Memory

Access (DMA) Controller Reference Guide (literature number SPRU587).

Table 3−6. DMA Sync Events

SYNC FIELD IN DMA_CCR

SYNC EVENT

00000b

No sync event

00001b

McBSP0 receive event (REVT0)

00010b

McBSP0 transmit event (XEVT0)

00101b

McBSP1 receive event (REVT1)

00110b

McBSP1 transmit event (XEVT1)

01001b

McBSP2 receive event (REVT2)

01010b

McBSP2 transmit event (XEVT2)

01101b

Timer 0 event

01110b

Timer 1 event

01111b

External Interrupt 0

10000b

External Interrupt 1

10001b

External Interrupt 2

10010b

External Interrupt 3

10011b

External Interrupt 4

10100b

External Interrupt 5

Other values

Reserved (do not use these values)

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