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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5510 датащи(PDF) 78 Page - Texas Instruments |
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TMS320VC5510 датащи(HTML) 78 Page - Texas Instruments |
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78 / 86 page  Electrical Specifications 78 June 2000 − Revised July 2004 SPRS076J Table 5−31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)†‡ NO. VC5510-160 VC5510-200 UNIT NO. MASTER SLAVE UNIT MIN MAX MIN MAX M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 4 3 − 6P ns M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 1 + 6P ns M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 10 ns M52 tc(CKX) Cycle time, CLKX 2P 16P ns † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. Table 5−32. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)†‡ NO. PARAMETER VC5510-160 VC5510-200 UNIT NO. PARAMETER MASTER§ SLAVE UNIT MIN MAX MIN MAX M43 td(CKXH-FXL) Delay time, FSX low to CLKX high¶ T − 1 T + 3 ns M44 td(FXL-CKXL) Delay time, FSX low to CLKX low# D − 2 D + 2 ns M45 td(CKXL-DXV) Delay time, CLKX low to DX valid −2 4 3P + 2 5P + 8 ns M46 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high D − 2 D ns M47 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 3P + 8 3P + 20 ns M48 td(FXL-DXV) Delay time, FSX low to DX valid 3P − 3 3P + 20 ns † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. § T = CLKX period = (1 + CLKGDV) * P D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). M51 M50 M47 M46 Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR M44 M48 M45 M49 M43 LSB MSB M52 Figure 5−26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 |
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