TMS320VC5510 datasheet(34/86 Pages) TI

34 / 86 page

Functional Overview

June 2000 − Revised July 2004

SPRS076J

3.4

Peripheral Register Description

Peripheral registers on the 5510 are accessed using the port qualifier. For more information on the use of the

port qualifier, see the TMS320C55x Assembly Language Tools User’s Guide (literature number SPRU280).

For detailed information on the operation of the peripherals and the functions of each of the peripheral

registers,

refer

the

TMS320C55x

DSP

Peripherals

Overview

Reference

Guide

(literature

number SPRU317).

NOTE: The CPU access latency to the peripheral memory-mapped registers is 6 CPU cycles.

Following peripheral register update(s), the CPU must wait at least 6 CPU cycles before

attempting to use that peripheral. When more than one peripheral register is updated in a

sequence, the CPU only needs to wait following the final register write. For example, if the

EMIF is being reconfigured, the CPU must wait until the very last EMIF register update takes

effect before trying to access the external memory. The users should consult the respective

peripheral user’s guide to determine if a peripheral requires additional time to initialize itself

to the new configuration after the register updates take effect.

Table 3−10. Peripheral Bus Controller Configuration Registers

PORT ADDRESS

DESCRIPTION

0x0001

ICR

Idle Control Register

0x0002

ISTR

Idle Status Register

0x000F

BOOT_MOD

Boot Mode Register (read only)

Table 3−11. Instruction Cache Registers

PORT ADDRESS

DESCRIPTION

0x1400

ICGC

I-Cache Global Control Register

0x1401

ICFL0

I-Cache Flush Line Address Register 0

0x1402

ICFL1

I-Cache Flush Line Address Register 1

0x1403

ICWC

I-Cache N-Way Control Register

0x1404

ICSTAT

I-Cache Status Register

0x1405

ICRC1

I-Cache Ramset 1 Control Register

0x1406

ICRTAG1

I-Cache Ramset 1 Tag Register

0x1407

ICRC2

I-Cache Ramset 2 Control Register

0x1408

ICRTAG2

I-Cache Ramset 2 Tag Register

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