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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320C6711 датащи(PDF) 2 Page - Texas Instruments |
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TMS320C6711 датащи(HTML) 2 Page - Texas Instruments |
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2 / 129 page  TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS088L − FEBRUARY 1999 − REVISED MAY 2004 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table of Contents bootmode 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range 64 . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 65 . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature for C6711/C6711B only 66 . . . . . . . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature for C6711C/C6711D only 67 . . . . . . . . . . . . . . . . . . . . . parameter measurement information 68 . . . . . . . . . . . . . . . signal transition levels 69 . . . . . . . . . . . . . . . . . . . . . . . . . . timing parameters and board routing analysis 69 . . . . . . input and output clocks 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 75 . . . . . . . . . . . . . . . . . . . . . synchronous-burst memory timing 79 . . . . . . . . . . . . . . . . . synchronous DRAM timing 83 . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA timing 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSREQ timing 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing [C6711/11B] 92 . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing [C6711C/11D] 94 . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing 96 . . . . . . . . . . . . . . . . . . . . . . . . . . host-port interface timing 97 . . . . . . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port timing 103 . . . . . . . . . . . . timer timing 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (GPIO) port timing [C6711C/C6711D only] 123 . . . . . . . . . . . . . . . . . . . . . JTAG test-port timing 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data [C6711/11B only] 125 . . . . . . . . . . . . . . . . mechanical data [C6711C/11D only] 126 . . . . . . . . . . . . . . . revision history 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GFN BGA package (bottom view) [C6711/11B only] 3 . . . . . . GDP BGA package (bottom view) [C6711C/11D only] 3 . . . . description 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device compatibility 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional block and CPU (DSP core) diagram 7 . . . . . . . . . . . CPU (DSP core) description 8 . . . . . . . . . . . . . . . . . . . . . . . . . . memory map summary 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral register descriptions 11 . . . . . . . . . . . . . . . . . . . . . . . signal groups description 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . device configurations 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . terminal functions 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU CSR register description 39 . . . . . . . . . . . . . . . . . . . . . . . . cache configuration (CCFG) register description (11D) 41 . . . interrupt sources and interrupt selector [C6711/11B only] 42 . interrupt sources and interrupt selector [11C/11D only] 43 . . . EDMA channel synchronization events [C6711/11B only] 44 . EDMA module and EDMA selector [C6711C/11D only] 45 . . . clock PLL [C6711/11B only] 47 . . . . . . . . . . . . . . . . . . . . . . . . . . PLL and PLL controller [C6711C/C6711D only] 49 . . . . . . . . . general-purpose input/output (GPIO) [11C/11D only 56 . . . . . power-down mode logic 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply decoupling 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 JTAG compatibility statement 61 . . . . . . . . . . . . . EMIF device speed (C6711/C6711B) 61 . . . . . . . . . . . . . . . . . . EMIF device speed (C6711C/C6711D only) 62 . . . . . . . . . . . . EMIF big endian mode correctness [C6711D only] 63 . . . . . . |
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