TMS320C6711 datasheet(67/129 Pages) TI

67 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

electrical characteristics over recommended ranges of supply voltage and operating case

temperature† (unless otherwise noted) for C6711C/C6711D only

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output

voltage (C6711C/11D)

All signals except CLKS1 and

DR1

DVDD = MIN, IOH = MAX

2.4

VOL

Low-level output

(C6711C/11D)

All signals except CLKS1 and

DR1

DVDD = MIN, IOL = MAX

0.4

VOL

voltage (C6711C/11D)

CLKS1 and DR1

DVDD = MIN, IOL = MAX

0.4

Input current

C6711C/11D: All signals except

CLKS1 and DR1

VI = VSS to DVDD

±170

Input current

C6711C/11D: CLKS1 and DR1

VI VSS to DVDD

±10

IOZ

Off-state output

current

C6711C/11D: All signals except

CLKS1 and DR1

VO = DVDD or 0 V

±170

IOZ

current

C6711C/11D: CLKS1 and DR1

VO DVDD or 0 V

±10

IDD2V

Core supply current‡

C6711D, CVDD = 1.4 V,

CPU clock = 250 MHz

810

Core supply current‡

C6711C, CVDD = 1.26 V,

CPU clock = 200 MHz

560

IDD2V

Core supply current‡

C6711D, CVDD = 1.26 V,

CPU clock = 200 MHz

560

Core supply current‡

C6711C, CVDD = 1.26 V,

CPU clock = 167 MHz

475

IDD2V

Core supply current‡

C6711D, CVDD = 1.26 V,

CPU clock = 167 MHz

475

IDD3V

I/O supply current‡

11C/11D, DVDD = 3.3 V,

EMIF speed = 100 MHz

Input capacitance

(C6711C/11D)

Output capacitance

(C6711C/11D)

† For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

‡ For the C6711C/C6711D device, these currents were measured with average activity (50% high/50% low power) at 25°C case temperature and

100-MHz EMIF. This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing

low-DSP-activity operations. The high/low-DSP-activity models are defined as follows:

High-DSP-Activity Model:

CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;

L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]

McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate

Low-DSP-Activity Model:

CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;

L2/EMIF EDMA: None]

McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate

The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6713/12C/11C Power

Consumption Summary

application report (literature number SPRA889).

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