TMS320C6711 datasheet(4/129 Pages) TI

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TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

description

The TMS320C67x DSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

devices†) compose the floating-point DSP family in the TMS320C6000 DSP platform. The C6711, C6711B,

C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word

(VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for

multichannel and multifunction applications.

With performance of up to 900 million floating-point operations per second (MFLOPS) at a clock rate of

150 MHz, the C6711/C6711B device offers cost-effective solutions to high-performance DSP programming

challenges. The C6711/C6711B DSP possesses the operational flexibility of high-speed controllers and the

numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length

and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs,

two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6711/C6711B can produce two MACs per

cycle for a total of 300 MMACS.

With performance of up to 1200 million floating-point operations per second (MFLOPS) at a clock rate of

200 MHz or 1350 MFLOPS at a clock rate of 250 MHz (for 6711D), the C6711C/C6711D device also offers

cost-effective solutions to high-performance DSP programming challenges. The C6711C/C6711D DSP also

possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.

This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional

units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two

floating-/fixed-point multipliers. The C6711C/C6711D can produce two MACs per cycle for a total of 400

MMACS.

The C6711/C6711B/C6711C/C6711D DSPs also have application-specific hardware logic, on-chip memory,

and additional on-chip peripherals.

The C6711/C6711B/C6711C/C6711D uses a two-level cache-based architecture and has a powerful and

diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level

1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a

512-Kbit memory space that is shared between program and data space. L2 memory can be configured as

mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered

serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory

interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6711/C6711B/C6711C/C6711D has a complete set of development tools which includes: a new C

compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface

for visibility into source code execution.

TMS320C6000 is a trademark of Texas Instruments.

Windows is a registered trademark of the Microsoft Corporation.

† Throughout the remainder of this document, the TMS320C6711, TMS320C6711B, TMS320C6711C, and TMS320C6711D shall be referred

to as TMS320C67x or C67x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6711,

C6711B, C6711C, C6711D, 11, 11B, 11C, or 11D, etc.

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