TMS320C6711 datasheet(81/129 Pages) TI

81 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

switching characteristics over recommended operating conditions for synchronous-burst SRAM

cycles†‡ (see Figure 32 and Figure 33) [C6711C/C6711D]

NO.

PARAMETER

GDPA-167

−200

−250 (6711D)

UNIT

MIN

MAX

td(EKOH-CEV)

Delay time, ECLKOUT high to CEx valid

1.2

td(EKOH-BEV)

Delay time, ECLKOUT high to BEx valid

td(EKOH-BEIV)

Delay time, ECLKOUT high to BEx invalid

1.2

td(EKOH-EAV)

Delay time, ECLKOUT high to EAx valid

td(EKOH-EAIV)

Delay time, ECLKOUT high to EAx invalid

1.2

td(EKOH-ADSV)

Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid

1.2

td(EKOH-OEV)

Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid

1.2

td(EKOH-EDV)

Delay time, ECLKOUT high to EDx valid

td(EKOH-EDIV)

Delay time, ECLKOUT high to EDx invalid

1.2

td(EKOH-WEV)

Delay time, ECLKOUT high to AWE/SDWE/SSWE valid

1.2

† The C6711/C6711B/C6711C/C6711D SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to

incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain

continuous data flow.

‡ ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM

accesses.

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