PCM3500ESLASH2K datasheet(25/26 Pages) TI

25 / 26 page

PCM3500

Software Modem AFE Application Circuit

Figure 25 shows an applications circuit which utilizes the

PCM3500 and the DAA2000 from Infineon Technologies

(Siemens) to implement a complete modem AFE. The

DAA2000 provides modem-side (DM207) and line-side

(DL207) interfaces, with optical isolation separating the

functions. The PCM3500 is connected to the modem-side of

the DAA2000. The PCM3500’s serial interface and hard-

ware mode controls are connected to the host CPU.

THEORY OF OPERATION

ADC SECTION

The PCM3500 A/D converter consists of two reference

circuits, a mono single-to-differential converter, a fully dif-

ferential 5th-order delta-sigma modulator, a decimation fil-

ter (including digital high pass), and a serial interface circuit.

The block diagram on the front page of this data sheet

illustrates the architecture of the ADC section, Figure 21

shows the single-to-differential converter, and Figure 26

illustrates the architecture of the 5th-order delta-sigma modu-

lator and transfer functions.

An internal reference circuit with three external capacitors

provides all reference voltages which are required by the

ADC, which defines the full-scale range for the converter.

The internal single-to-differential voltage converter saves

the design, space and extra parts needed for external cir-

cuitry required by many delta-sigma converters. The internal

full-differential signal processing architecture provides a

wide dynamic range and excellent power supply rejection

performance. The input signal is sampled at a 64x

oversampling rate, eliminating the need for a sample-and-

hold circuit, and simplifying anti-alias filtering require-

ments. The 5th-order delta-sigma noise shaper consists of

five integrators which use a switched-capacitor topology, a

comparator, and a feedback loop consisting of a one-bit

DAC. The delta-sigma modulator shapes the quantization

noise, shifting it out of the audio band in the frequency

domain. The high order of the modulator enables it to

randomize the modulator outputs, reducing idle tone levels.

The 64fS one-bit data stream from the modulator is con-

verted to 1fS, 16-bit data words by the decimation filter,

which also acts as a low-pass filter to remove the shaped

quantization noise. The DC components can be removed by

a high-pass filter function contained within the decimation

filter.

DAC SECTION

The delta-sigma DAC section of PCM3500 is based on a 5-

level amplitude quantizer and a 3rd-order noise shaper. This

section converts the oversampled input data to 5-level delta-

sigma format. A block diagram of the 5-level delta-sigma

modulator is shown in Figure 27. This 5-level delta-sigma

modulator has the advantage of stability and clock jitter

sensitivity over the typical one-bit (2 level) delta-sigma

modulator. The combined oversampling rate of the delta-

sigma modulator and the internal 8x interpolation filter is

64fS for a 512fS system clock. The theoretical quantization

noise performance of the 5-level delta-sigma modulator is

shown in Figure 28.

–

5th SW-CAP

Integrator

4th SW-CAP

Integrator

3rd SW-CAP

Integrator

2nd SW-CAP

Integrator

1st SW-CAP

Integrator

–

1-Bit

DAC

H(z)

Qn(z)

Analog In

X(z)

Digital Out

Y(z)

Y(z) = STF(z) • X(z) + NTF(z) • Qn(z)

Signal Transfer Function

Noise Transfer Function

STF(z) = H(z) / [1 + H(z)]

NTF(z) = 1/ [1 + H(z)]

Comparator

FIGURE 26. Simplified 5th-Order Delta-Sigma Modulator.

PCM3500E/2K датащи(PDF) 25 Page - Texas Instruments

PCM3500E/2K датащи(HTML) 25 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

датащи скачать

ссылки URL