®

14

PCM3500

SERIAL INTERFACE

The serial interface of the PCM3500 is a 4-wire synchronous

serial port. It includes FS (pin 9), BCK (pin 8), DIN (pin 10)

and DOUT (pin 11). FS is the frame synchronization clock,

BCK is the serial bit or shift clock, DIN is the serial data input

for the DAC, and DOUT is the serial data output for the ADC.

DIN and DOUT also operate at the bit clock rate. Both FS

and BCK must be synchronous with the system clock (guar-

anteed in Master Mode). Data for DIN is clocked into the

serial interface on the rising edge of BCK, while data for

DOUT is clocked out of the serial interface on the falling

edge of BCK.

Figure 6 shows the serial interface format for the PCM3500.

The serial data for DIN and DOUT must be in Binary Two’s

Complement, MSB-first format. Figures 7 and 8 show the

timing specifications for the serial interface when used in

Slave and Master Modes.

FS

BCK

DIN

DOUT

MSB

MSB

LSB

LSB

MSB

MSB

LSB

LSB

15 14 13 12 11

21

0

54

3

15 14 13 12 11

21

0

54

3

15 14 13 12 11

21

0

54

3

15 14 13 12 11

21

0

54

3

1/f

S

16-Bit/Frame

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

BCK Period

2400

ns

BCK Pulse Width HIGH

800

ns

BCK Pulse Width LOW

800

ns

FS Pulse Width HIGH

ns

FS Period

FS Set Up Time to BCK Rising Edge

60

ns

FS Hold Time to BCK Rising Edge

60

ns

DIN Set Up Time to BCK Rising Edge

60

ns

DIN Hold Time to BCK Rising Edge

60

ns

Delay Time BCK Falling Edge to DOUT

0

80

ns

Rising Time of All Signals

30

ns

Falling Time of All Signals

30

ns

FIGURE 6. Serial Interface Format.

FIGURE 7. Serial Interface Timing for Slave Mode.

t

FSW

t

FSSU

t

FSHD

t

BCKP

t

BCKH

t

DISU

t

DIHD

t

BCKL

t

CKDO

t

FSP

FS

(input)

BCK

(input)

DIN

(input)

DOUT

(output)

NOTES: Timing measurement reference level is (VIH/VIL)/2. RIsing and falling time is measured

from 10% to 90% of IN/OUT signal swing. Load capacitance of DOUT signal is 50pF.

0.5V

DD

0.5V

DD

0.5V

DD

0.5V

DD