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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PCM3500E/2K датащи(PDF) 16 Page - Texas Instruments |
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PCM3500E/2K датащи(HTML) 16 Page - Texas Instruments |
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16 / 26 page  ® 16 PCM3500 SYNCHRONIZATION REQUIREMENTS The PCM3500 requires that FS and BCK be synchronous with the system clock. Internal circuitry is included to detect a loss of synchronization between FS and the system clock input. If the phase relationship between FS and the system clock varies more than ± 1.5 BCK periods, the PCM3500 will detect a loss of synchronization. Upon detection, the DAC output is forced to 0.5VCC and the DOUT pin is forced to a high impedance state. This occurs within one sampling clock (FS) period of initial detection. Figure 10 shows the loss of synchronization operation and the DAC and ADC output delays associated with it. TIME SLOT OPERATION The PCM3500 serial interface supports Time Division Multiplexing (TDM) using the Time Slot Mode. Up to four PCM3500s may be connected on the same 4-wire serial interface bus. This is useful for system applications that require multiple modem or voice channels. Figure 11 shows examples of Time Slot Mode connections. Time Slot Mode defines a 64-bit long frame, composed of four time slots. Each slot is 16 bits long and corresponds to one of four CODECs. The FS pin on the first PCM3500 (CODEC A, Slot 0) is used as the master frame sync, and operates at the sampling frequency, fS. The bit clock, BCK, operates at 64fS. DIN and DOUT of each CODEC also operate at 64fS. Figure 12 shows the operation of the Time Slot Mode. Time Slot operation is enabled or disabled using the TSC input (pin 7). The state of the TSC pin is updated at power- on reset, or on the rising edge of PWDN input (if using external reset or power-down mode). A forced reset is required when changing from Slave to Master Mode, or visa versa, in real time. FIGURE 10. Loss of Synchronization Operation and Timing. FIGURE 11. Time Slot Mode Connections. Synchronous Asynchronous Synchronization Lost Resynchronization within 1/f S Synchronous Normal Normal t ADCDLY2 (32/fS) t DACDLY2 (32/fS) V COM (0.5 V CC) V COM (0.5 V CC) State of Synchronization DAC V OUT Normal Normal(1) High Impedance ADC DOUT NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR with 200ms time constant) appears initially. Undefined Data Undefined Data V DD V DD Controller GND V DD SCKIO XTI XTO FS BCK DIN DOUT FSO M/S TSC PCM3500 (CODEC B, Slot 1) PCM3500 (CODEC A, Slot 0) To Two PCM3500s SCKIO XTI XTO FS BCK DIN DOUT FSO M/S TSC |
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