PC87591L datasheet(115/437 Pages) NSC

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Embedded Controller Modules (Continued)

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Output Buffer

The output buffer is a TRI-STATE buffer. The output type (i.e., CMOS or TTL) and its driving capabilities are described in

Section 2.2 on page 41.

Input Buffer

The I/O port input buffer characteristics are defined in Section 2.2 on page 41.

The input buffer has an enable input. When enabled, the buffer inputs the pin’s logic level to the on-chip modules. When

disabled, the input is blocked to prevent supply leakage currents.

Weak Pull-Up

The weak pull-up is enabled when the corresponding bit of PxWPU is set (1) and the pin is configured as an input port. When

the pin is configured for input, this pull-up can prevent the input from being in an undefined state. When the pin is configured

as an output port, this pull-up is disabled.

Alternate Function

The PxALT controls the use of each of the port pins for GPIO or for the pin’s respective alternate function.

When PxALT bit is cleared (0):

●

The corresponding pin is used as a GPIO pin.

●

The output buffer is controlled by the Direction and Data Output registers.

●

The input buffer is routed to the Data Input register.

In this case, the input buffer is blocked, except when the buffer is actually being read.

●

The pull-up is enabled when both the PxWPU is set and the device puts the output buffer in TRI-STATE.

When a bit in PxALT is set (1):

●

The corresponding pin is used for an alternate function (i.e., a signal from/to some other PC87591x module).

●

The output buffer data and TRI-STATE are controlled by signals from the alternate module.

●

The input buffer is always enabled when the alternate function is an input; therefore, to minimize current consump-

tion, the signal should be held above VCC−0.2 or below GND+0.2V.

●

The pull-up is enabled when PxWPU is set and the device puts the output buffer in TRI-STATE.

Port Direction

The Port Direction register (PxDIR) controls the direction of the port. If set (1), each bit in the register causes the correspond-

ing port signal to serve as an output port, thus enabling the output buffer.

When cleared, the port serves as an input port signal, thus putting the output buffer in TRI-STATE.

If the corresponding bit in PxWPU is set, it also enables the pull-up.

Data Output

The Data Output (PxDOUT) register holds the data to be driven onto the pin, when the respective pin is configured as GPIO

and its direction is set as output.

Data Input

The Data Input (PxDIN) register returns the current value/state of the pin. This register can always be read.

Open Drain

To use the GPIO pin as an inverting open-drain output buffer, the software should clear the corresponding bit in PxDOUT

When the signal direction is set as output (1), a value of 0 is forced. When the direction is set for input (0), the signal is in

TRI-STATE and is not forced low.

The internal weak pull-up can pull the signal high when it is not forced low, by writing (1) to the corresponding bit of PxWPU.

Input Echo Function

Some of the Px pins can echo the value of an input pin. Figure 34 illustrates the modified structure of Px port pins that support

the echo function. The input echo function may be used when the Px pin is configured to operate as a General-Purpose

output pin.

Table 9 on page 60 defines pairs of input ports (Pi) and output ports (Po) and the Echo Enable bit associated with each pair.

When the pair’s Echo Enable bit is set, and if Po is configured as output, the value from the input bit (Pi) is output to the

respective output port (Po). When the pair’s Echo Enable bit is cleared, and if Po is configured as output, the value in

PxDOUT is output to the respective output port.

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