PC87591L datasheet(118/437 Pages) NSC

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Embedded Controller Modules (Continued)

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Data Output

The Data Out (PzDOUT) register holds the data to be driven onto the pin.

4.5.5

GPIO Port Pw

GPIO Port Signals Shared with Development System Signals

The Pw GPIO port enables access to input and output pins. Depending on the operating environments, some pins of the I/O

ports may be dedicated to functions other than input or output. In this case, low-cost external logic can be used to perform

the I/O functions with binary and cycle-by-cycle compatibility (see Section 4.1.8 on page 80 for details of the Expansion I/O

protocol). The Alternate Functions Table (Table 8 on page 54) defines the environment in which each port is implemented

off-chip and the pin that performs its alternate function.

The I/O Expansion protocol is used to access the off-chip implementation of the port’s registers (PwDIR, PwDOUT, PwDIN),

when the port pins are used by DEV environment. This enables binary compatibility between all environments.

To enable cycle-by-cycle compatibility in all environments, the access time to any of the registers is identical for on-chip and

off-chip implementation of the ports (i.e., as configured for the BIU I/O zone).

Figure 37 illustrates its functionality.

Output Buffer

The output buffer is a TRI-STATE buffer. Its output type (i.e., CMOS or TTL) and its driving capabilities are described in

Section 2.2 on page 41.

Input Buffer

The I/O port input buffer characteristics are defined in Section 2.2 on page 41. The input buffer has an enable input. When

enabled, the buffer inputs the pin’s logic level to the on-chip modules. When disabled, the input is blocked to prevent supply

leakage currents.

Port Direction

The Port Direction register (PwDIR) controls the direction of the port. When set (1), each bit in PwDIR register causes the

corresponding port signal to serve as an output port, thus enabling the output buffer. When cleared, the port serves as an

input port signal, thus putting the output buffer in TRI-STATE.

Data Output

The Data Output (PwDOUT) register holds the data to be driven onto the pin when the corresponding pin is set as GPIO and

its direction is set as output.

Data Input

The Data Input (PwDIN) register returns the current value/state of the pin. This register can always be read.

Open Drain

To use the GPIO pin as an inverting open-drain output buffer, the software should clear the corresponding bit in Data Output

(PwDOUT) register and then use the Direction register to set the value to the port pin.

Data Output

{

Direction

{

Data Input Register

Data Input Read

Data Out

(PwDOUT)

Direction

(PwDIR)

PwDIN

Figure 37. GPIO Port Pw Schematic Diagram

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