PC87591L datasheet(111/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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Pending Register (WKPND4)

Byte-wide read/write register that latches the occurrence of a selected trigger condition associated with the input signals

WUI40 to WUI47. For a detailed description of the register see the above description of the WKPND1 register.

Location: 00 FFD416

Type: R/W

Enable Register (WKEN1)

Byte-wide read/write register that enables the wake-up function of the associated input signal, WUI10 to WUI17. On reset,

WDENA1 is cleared (0); this disables the associated input signals. The WKENA1 register format is shown below:

Location: 00 FFD816

Type: R/W

Enable Register (WKEN2)

Byte-wide read/write register that enables the wake-up function of the associated input signal, WUI20 to WUI27. For a de-

tailed description of the register, see the above description of the WKEN1 register.

Location: 00 FFDA16

Type: R/W

Enable Register (WKEN3)

Byte-wide read/write register that enables the wake-up function of the associated input signal, WUI30 to WUI37. For a de-

tailed description of the register, see the above description of the WKEN1 register.

Location: 00 FFDC16

Type: R/W

Enable Register (WKEN4)

Byte-wide read/write register that enables the wake-up function of the associated input signal, WUI40 to WUI47. For a de-

tailed description of the register, see the above description of the WKEN1 register.

Location: 00 FFDE16

Type: R/W

Pending Clear Register (WKPCL1)

Byte-wide write-only register that controls the clearing (0) of the pending bits associated with the WUI10 through WUI17 in-

puts. This avoids potential hardware/software collisions during read-modify-write operations. The WKPCL1 register format

is shown below:

Location: 00 FFCA16

Type: WO

Bit

76543210

Name

WKEN17-WKEN10

Reset

00000000

Bit

Description

7-0

Wake-Up Enable. If set (1), a valid trigger condition on the associated input generates a wake-up signal or

EXTINTx interrupt request

Bit

76543210

Name

WKCL17-WKCL10

Bit

Description

7-0

Clear Pending Flag. If a 1 is written to any bit, the associated pending ﬂag located in WKPND1 is cleared (0).

Writing a 0 to any bit leaves the value of the corresponding pending ﬂag unchanged.

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